mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
262 lines
7.7 KiB
C
262 lines
7.7 KiB
C
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/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MXC_MX51_H__
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#define __ASM_ARCH_MXC_MX51_H__
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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/*
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* IRAM
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*/
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#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
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/*
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* Graphics Memory of GPU
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*/
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#define GPU_BASE_ADDR 0x20000000
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#define GPU_CTRL_BASE_ADDR 0x30000000
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#define IPU_CTRL_BASE_ADDR 0x40000000
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/*
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* Debug
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*/
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#define DEBUG_BASE_ADDR 0x60000000
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#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
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#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
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#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
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#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
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#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
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#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
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#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
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#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
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/*
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* SPBA global module enabled #0
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*/
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#define SPBA0_BASE_ADDR 0x70000000
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#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
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#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
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#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
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#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
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#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
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#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
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#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
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#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
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#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
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#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
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#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
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#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
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/*
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* AIPS 1
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*/
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#define AIPS1_BASE_ADDR 0x73F00000
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#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
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#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
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#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
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#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
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#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
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#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
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#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
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#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
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#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
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#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
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#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
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#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
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#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
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#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
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#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
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#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
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#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
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#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
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#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
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#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
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/*
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* AIPS 2
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*/
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#define AIPS2_BASE_ADDR 0x83F00000
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#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
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#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
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#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
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#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
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#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
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#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
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#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
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#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
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#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
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#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
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#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
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#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
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#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
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#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
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#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
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#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
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#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
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#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
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#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
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#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
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#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
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#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
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#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
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#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
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#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
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#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
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#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
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#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
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#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
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#define TZIC_BASE_ADDR 0x8FFFC000
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/*
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* Memory regions and CS
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*/
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#define CSD0_BASE_ADDR 0x90000000
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#define CSD1_BASE_ADDR 0xA0000000
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#define CS0_BASE_ADDR 0xB0000000
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#define CS1_BASE_ADDR 0xB8000000
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#define CS2_BASE_ADDR 0xC0000000
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#define CS3_BASE_ADDR 0xC8000000
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#define CS4_BASE_ADDR 0xCC000000
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#define CS5_BASE_ADDR 0xCE000000
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/*
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* NFC
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*/
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#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
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/*!
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* Number of GPIO port as defined in the IC Spec
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*/
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#define GPIO_PORT_NUM 4
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/*!
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* Number of GPIO pins per port
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*/
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#define GPIO_NUM_PIN 32
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#define IIM_SREV 0x24
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#define ROM_SI_REV 0x48
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#define NFC_BUF_SIZE 0x1000
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/* M4IF */
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#define M4IF_FBPM0 0x40
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#define M4IF_FIDBP 0x48
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/* Assuming 24MHz input clock with doubler ON */
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/* MFI PDF */
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#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
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#define DP_MFD_850 (48 - 1)
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#define DP_MFN_850 41
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#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
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#define DP_MFD_800 (3 - 1)
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#define DP_MFN_800 1
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#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
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#define DP_MFD_700 (24 - 1)
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#define DP_MFN_700 7
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#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
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#define DP_MFD_665 (96 - 1)
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#define DP_MFN_665 89
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#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
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#define DP_MFD_532 (24 - 1)
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#define DP_MFN_532 13
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#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
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#define DP_MFD_400 (3 - 1)
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#define DP_MFN_400 1
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#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
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#define DP_MFD_216 (4 - 1)
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#define DP_MFN_216 3
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_2_0 0x20
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#define CHIP_REV_2_5 0x25
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#define CHIP_REV_3_0 0x30
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#ifndef __ASSEMBLY__
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struct clkctl {
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u32 ccr;
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u32 ccdr;
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u32 csr;
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u32 ccsr;
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u32 cacrr;
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u32 cbcdr;
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u32 cbcmr;
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u32 cscmr1;
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u32 cscmr2;
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u32 cscdr1;
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u32 cs1cdr;
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u32 cs2cdr;
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u32 cdcdr;
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u32 chsccdr;
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u32 cscdr2;
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u32 cscdr3;
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u32 cscdr4;
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u32 cwdr;
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u32 cdhipr;
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u32 cdcr;
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u32 ctor;
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u32 clpcr;
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u32 cisr;
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u32 cimr;
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u32 ccosr;
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u32 cgpr;
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u32 ccgr0;
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u32 ccgr1;
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u32 ccgr2;
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u32 ccgr3;
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u32 ccgr4;
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u32 ccgr5;
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u32 ccgr6;
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u32 cmeor;
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};
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/* WEIM registers */
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struct weim {
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u32 csgcr1;
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u32 csgcr2;
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u32 csrcr1;
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u32 csrcr2;
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u32 cswcr1;
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u32 cswcr2;
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};
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#endif /* __ASSEMBLER__*/
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#endif /* __ASM_ARCH_MXC_MX51_H__ */
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