2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2008-10-21 10:03:07 +00:00
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/*
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* Message Digest Hardware Accelerator Memory Map
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __MDHA_H__
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#define __MDHA_H__
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/* Message Digest Hardware Accelerator */
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typedef struct mdha_ctrl {
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u32 mr; /* 0x00 MDHA Mode */
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u32 cr; /* 0x04 Control */
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u32 cmd; /* 0x08 Command */
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u32 sr; /* 0x0C Status */
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u32 isr; /* 0x10 Interrupt Status */
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u32 imr; /* 0x14 Interrupt Mask */
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u32 dsz; /* 0x1C Data Size */
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u32 inp; /* 0x20 Input FIFO */
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u32 res1[3]; /* 0x24 - 0x2F */
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u32 mda0; /* 0x30 Message Digest AO */
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u32 mdb0; /* 0x34 Message Digest BO */
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u32 mdc0; /* 0x38 Message Digest CO */
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u32 mdd0; /* 0x3C Message Digest DO */
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u32 mde0; /* 0x40 Message Digest EO */
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u32 mdsz; /* 0x44 Message Data Size */
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u32 res[10]; /* 0x48 - 0x6F */
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u32 mda1; /* 0x70 Message Digest A1 */
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u32 mdb1; /* 0x74 Message Digest B1 */
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u32 mdc1; /* 0x78 Message Digest C1 */
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u32 mdd1; /* 0x7C Message Digest D1 */
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u32 mde1; /* 0x80 Message Digest E1 */
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} mdha_t;
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#define MDHA_MR_SSL (0x00000400)
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#define MDHA_MR_MACFUL (0x00000200)
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#define MDHA_MR_SWAP (0x00000100)
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#define MDHA_MR_OPAD (0x00000080)
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#define MDHA_MR_IPAD (0x00000040)
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#define MDHA_MR_INIT (0x00000020)
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#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
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#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
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#define MDHA_MR_MAC_EHMAC (0x00000010)
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#define MDHA_MR_MAC_HMAC (0x00000008)
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#define MDHA_MR_MAC_NONE (0x00000000)
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#define MDHA_MR_PDATA (0x00000004)
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#define MDHA_MR_ALG (0x00000001)
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#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
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#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
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#define MDHA_CR_END (0x00000004) /* 532x */
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#define MDHA_CR_DMA (0x00000002) /* 532x */
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#define MDHA_CR_IE (0x00000001)
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#define MDHA_CMD_GO (0x00000008)
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#define MDHA_CMD_CI (0x00000004)
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#define MDHA_CMD_RI (0x00000001)
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#define MDHA_CMD_SWR (0x00000001)
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#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
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#define MDHA_SR_IFL_MASK (0xFF00FFFF)
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#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
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#define MDHA_SR_APD_MASK (0xFFFF1FFF)
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#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
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#define MDHA_SR_FS_MASK (0xFFFFF8FF)
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#define MDHA_SR_GNW (0x00000080)
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#define MDHA_SR_HSH (0x00000040)
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#define MDHA_SR_BUSY (0x00000010)
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#define MDHA_SR_RD (0x00000008)
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#define MDHA_SR_ERR (0x00000004)
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#define MDHA_SR_DONE (0x00000002)
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#define MDHA_SR_INT (0x00000001)
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#define MDHA_ISR_DRL (0x00000400) /* 532x */
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#define MDHA_ISR_GTDS (0x00000200)
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#define MDHA_ISR_ERE (0x00000100)
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#define MDHA_ISR_RMDP (0x00000080)
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#define MDHA_ISR_DSE (0x00000020)
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#define MDHA_ISR_IME (0x00000010)
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#define MDHA_ISR_NEIF (0x00000004)
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#define MDHA_ISR_IFO (0x00000001)
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#endif /* __MDHA_H__ */
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