2020-01-10 08:30:27 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dm.h>
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#include "pinctrl-mtk-common.h"
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#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
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#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 32, 0)
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#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 32, 1)
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static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
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PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
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PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
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PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
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PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
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PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
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PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
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PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
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PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
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PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
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PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
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PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
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PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
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PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
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PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
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PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
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PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
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PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
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PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
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PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
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PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
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PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
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PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
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PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
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PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
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PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
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PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
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};
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static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
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PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
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PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
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PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
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PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
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PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
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PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
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PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
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PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
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PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
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PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
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PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
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PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
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PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
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PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
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PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
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PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
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PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
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PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
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PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
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PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
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PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
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PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
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PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
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PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
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PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
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PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
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PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
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PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
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PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
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PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
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PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
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};
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static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
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PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
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PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
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PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
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PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
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PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
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PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
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PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
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};
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static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
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[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
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[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
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[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
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[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
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[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
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[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
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[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
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[PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
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[PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
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};
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static const struct mtk_pin_desc mt7622_pins[] = {
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MT7622_PIN(0, "GPIO_A"),
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MT7622_PIN(1, "I2S1_IN"),
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MT7622_PIN(2, "I2S1_OUT"),
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MT7622_PIN(3, "I2S_BCLK"),
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MT7622_PIN(4, "I2S_WS"),
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MT7622_PIN(5, "I2S_MCLK"),
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MT7622_PIN(6, "TXD0"),
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MT7622_PIN(7, "RXD0"),
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MT7622_PIN(8, "SPI_WP"),
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MT7622_PIN(9, "SPI_HOLD"),
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MT7622_PIN(10, "SPI_CLK"),
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MT7622_PIN(11, "SPI_MOSI"),
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MT7622_PIN(12, "SPI_MISO"),
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MT7622_PIN(13, "SPI_CS"),
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MT7622_PIN(14, "I2C_SDA"),
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MT7622_PIN(15, "I2C_SCL"),
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MT7622_PIN(16, "I2S2_IN"),
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MT7622_PIN(17, "I2S3_IN"),
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MT7622_PIN(18, "I2S4_IN"),
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MT7622_PIN(19, "I2S2_OUT"),
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MT7622_PIN(20, "I2S3_OUT"),
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MT7622_PIN(21, "I2S4_OUT"),
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MT7622_PIN(22, "GPIO_B"),
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MT7622_PIN(23, "MDC"),
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MT7622_PIN(24, "MDIO"),
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MT7622_PIN(25, "G2_TXD0"),
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MT7622_PIN(26, "G2_TXD1"),
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MT7622_PIN(27, "G2_TXD2"),
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MT7622_PIN(28, "G2_TXD3"),
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MT7622_PIN(29, "G2_TXEN"),
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MT7622_PIN(30, "G2_TXC"),
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MT7622_PIN(31, "G2_RXD0"),
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MT7622_PIN(32, "G2_RXD1"),
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MT7622_PIN(33, "G2_RXD2"),
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MT7622_PIN(34, "G2_RXD3"),
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MT7622_PIN(35, "G2_RXDV"),
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MT7622_PIN(36, "G2_RXC"),
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MT7622_PIN(37, "NCEB"),
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MT7622_PIN(38, "NWEB"),
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MT7622_PIN(39, "NREB"),
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MT7622_PIN(40, "NDL4"),
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MT7622_PIN(41, "NDL5"),
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MT7622_PIN(42, "NDL6"),
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MT7622_PIN(43, "NDL7"),
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MT7622_PIN(44, "NRB"),
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MT7622_PIN(45, "NCLE"),
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MT7622_PIN(46, "NALE"),
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MT7622_PIN(47, "NDL0"),
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MT7622_PIN(48, "NDL1"),
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MT7622_PIN(49, "NDL2"),
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MT7622_PIN(50, "NDL3"),
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MT7622_PIN(51, "MDI_TP_P0"),
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MT7622_PIN(52, "MDI_TN_P0"),
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MT7622_PIN(53, "MDI_RP_P0"),
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MT7622_PIN(54, "MDI_RN_P0"),
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MT7622_PIN(55, "MDI_TP_P1"),
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MT7622_PIN(56, "MDI_TN_P1"),
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MT7622_PIN(57, "MDI_RP_P1"),
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MT7622_PIN(58, "MDI_RN_P1"),
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MT7622_PIN(59, "MDI_RP_P2"),
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MT7622_PIN(60, "MDI_RN_P2"),
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MT7622_PIN(61, "MDI_TP_P2"),
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MT7622_PIN(62, "MDI_TN_P2"),
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MT7622_PIN(63, "MDI_TP_P3"),
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MT7622_PIN(64, "MDI_TN_P3"),
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MT7622_PIN(65, "MDI_RP_P3"),
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MT7622_PIN(66, "MDI_RN_P3"),
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MT7622_PIN(67, "MDI_RP_P4"),
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MT7622_PIN(68, "MDI_RN_P4"),
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MT7622_PIN(69, "MDI_TP_P4"),
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MT7622_PIN(70, "MDI_TN_P4"),
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MT7622_PIN(71, "PMIC_SCL"),
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MT7622_PIN(72, "PMIC_SDA"),
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MT7622_PIN(73, "SPIC1_CLK"),
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MT7622_PIN(74, "SPIC1_MOSI"),
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MT7622_PIN(75, "SPIC1_MISO"),
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MT7622_PIN(76, "SPIC1_CS"),
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MT7622_PIN(77, "GPIO_D"),
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MT7622_PIN(78, "WATCHDOG"),
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MT7622_PIN(79, "RTS3_N"),
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MT7622_PIN(80, "CTS3_N"),
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MT7622_PIN(81, "TXD3"),
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MT7622_PIN(82, "RXD3"),
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MT7622_PIN(83, "PERST0_N"),
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MT7622_PIN(84, "PERST1_N"),
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MT7622_PIN(85, "WLED_N"),
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MT7622_PIN(86, "EPHY_LED0_N"),
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MT7622_PIN(87, "AUXIN0"),
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MT7622_PIN(88, "AUXIN1"),
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MT7622_PIN(89, "AUXIN2"),
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MT7622_PIN(90, "AUXIN3"),
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MT7622_PIN(91, "TXD4"),
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MT7622_PIN(92, "RXD4"),
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MT7622_PIN(93, "RTS4_N"),
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MT7622_PIN(94, "CTS4_N"),
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MT7622_PIN(95, "PWM1"),
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MT7622_PIN(96, "PWM2"),
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MT7622_PIN(97, "PWM3"),
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MT7622_PIN(98, "PWM4"),
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MT7622_PIN(99, "PWM5"),
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MT7622_PIN(100, "PWM6"),
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MT7622_PIN(101, "PWM7"),
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MT7622_PIN(102, "GPIO_E"),
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};
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/* List all groups consisting of these pins dedicated to the enablement of
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* certain hardware block and the corresponding mode for all of the pins. The
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* hardware probably has multiple combinations of these pinouts.
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*/
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/* EMMC */
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static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
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static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
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static int mt7622_emmc_rst_pins[] = { 37, };
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static int mt7622_emmc_rst_funcs[] = { 1, };
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/* LED for EPHY */
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static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
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static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
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static int mt7622_ephy0_led_pins[] = { 86, };
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static int mt7622_ephy0_led_funcs[] = { 0, };
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static int mt7622_ephy1_led_pins[] = { 91, };
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static int mt7622_ephy1_led_funcs[] = { 2, };
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static int mt7622_ephy2_led_pins[] = { 92, };
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static int mt7622_ephy2_led_funcs[] = { 2, };
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static int mt7622_ephy3_led_pins[] = { 93, };
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static int mt7622_ephy3_led_funcs[] = { 2, };
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static int mt7622_ephy4_led_pins[] = { 94, };
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static int mt7622_ephy4_led_funcs[] = { 2, };
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/* Embedded Switch */
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static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
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62, 63, 64, 65, 66, 67, 68, 69, 70, };
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static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, };
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static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
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static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
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static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
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68, 69, 70, };
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static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, };
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/* RGMII via ESW */
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static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
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67, 68, 69, 70, };
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static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, };
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/* RGMII via GMAC1 */
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static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
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67, 68, 69, 70, };
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static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, };
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/* RGMII via GMAC2 */
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static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, };
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static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, };
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/* I2C */
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static int mt7622_i2c0_pins[] = { 14, 15, };
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static int mt7622_i2c0_funcs[] = { 0, 0, };
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static int mt7622_i2c1_0_pins[] = { 55, 56, };
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static int mt7622_i2c1_0_funcs[] = { 0, 0, };
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static int mt7622_i2c1_1_pins[] = { 73, 74, };
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static int mt7622_i2c1_1_funcs[] = { 3, 3, };
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static int mt7622_i2c1_2_pins[] = { 87, 88, };
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static int mt7622_i2c1_2_funcs[] = { 0, 0, };
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static int mt7622_i2c2_0_pins[] = { 57, 58, };
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static int mt7622_i2c2_0_funcs[] = { 0, 0, };
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static int mt7622_i2c2_1_pins[] = { 75, 76, };
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static int mt7622_i2c2_1_funcs[] = { 3, 3, };
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static int mt7622_i2c2_2_pins[] = { 89, 90, };
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static int mt7622_i2c2_2_funcs[] = { 0, 0, };
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/* I2S */
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static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
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static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
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static int mt7622_i2s1_in_data_pins[] = { 1, };
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static int mt7622_i2s1_in_data_funcs[] = { 0, };
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static int mt7622_i2s2_in_data_pins[] = { 16, };
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static int mt7622_i2s2_in_data_funcs[] = { 0, };
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static int mt7622_i2s3_in_data_pins[] = { 17, };
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static int mt7622_i2s3_in_data_funcs[] = { 0, };
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static int mt7622_i2s4_in_data_pins[] = { 18, };
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static int mt7622_i2s4_in_data_funcs[] = { 0, };
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static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
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static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
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static int mt7622_i2s1_out_data_pins[] = { 2, };
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static int mt7622_i2s1_out_data_funcs[] = { 0, };
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static int mt7622_i2s2_out_data_pins[] = { 19, };
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static int mt7622_i2s2_out_data_funcs[] = { 0, };
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static int mt7622_i2s3_out_data_pins[] = { 20, };
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static int mt7622_i2s3_out_data_funcs[] = { 0, };
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static int mt7622_i2s4_out_data_pins[] = { 21, };
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static int mt7622_i2s4_out_data_funcs[] = { 0, };
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/* IR */
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static int mt7622_ir_0_tx_pins[] = { 16, };
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static int mt7622_ir_0_tx_funcs[] = { 4, };
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static int mt7622_ir_1_tx_pins[] = { 59, };
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static int mt7622_ir_1_tx_funcs[] = { 5, };
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static int mt7622_ir_2_tx_pins[] = { 99, };
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static int mt7622_ir_2_tx_funcs[] = { 3, };
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static int mt7622_ir_0_rx_pins[] = { 17, };
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static int mt7622_ir_0_rx_funcs[] = { 4, };
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static int mt7622_ir_1_rx_pins[] = { 60, };
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static int mt7622_ir_1_rx_funcs[] = { 5, };
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static int mt7622_ir_2_rx_pins[] = { 100, };
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static int mt7622_ir_2_rx_funcs[] = { 3, };
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/* MDIO */
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static int mt7622_mdc_mdio_pins[] = { 23, 24, };
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static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
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/* PCIE */
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static int mt7622_pcie0_0_waken_pins[] = { 14, };
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static int mt7622_pcie0_0_waken_funcs[] = { 2, };
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static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
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static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
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static int mt7622_pcie0_1_waken_pins[] = { 79, };
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static int mt7622_pcie0_1_waken_funcs[] = { 4, };
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static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
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static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
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static int mt7622_pcie1_0_waken_pins[] = { 14, };
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static int mt7622_pcie1_0_waken_funcs[] = { 3, };
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static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
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static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
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static int mt7622_pcie0_pad_perst_pins[] = { 83, };
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static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
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static int mt7622_pcie1_pad_perst_pins[] = { 84, };
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static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
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/* PMIC bus */
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static int mt7622_pmic_bus_pins[] = { 71, 72, };
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static int mt7622_pmic_bus_funcs[] = { 0, 0, };
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/* Parallel NAND */
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static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, };
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|
static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, };
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/* PWM */
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static int mt7622_pwm_ch1_0_pins[] = { 51, };
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static int mt7622_pwm_ch1_0_funcs[] = { 3, };
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static int mt7622_pwm_ch1_1_pins[] = { 73, };
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static int mt7622_pwm_ch1_1_funcs[] = { 4, };
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static int mt7622_pwm_ch1_2_pins[] = { 95, };
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static int mt7622_pwm_ch1_2_funcs[] = { 0, };
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static int mt7622_pwm_ch2_0_pins[] = { 52, };
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static int mt7622_pwm_ch2_0_funcs[] = { 3, };
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static int mt7622_pwm_ch2_1_pins[] = { 74, };
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static int mt7622_pwm_ch2_1_funcs[] = { 4, };
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static int mt7622_pwm_ch2_2_pins[] = { 96, };
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static int mt7622_pwm_ch2_2_funcs[] = { 0, };
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static int mt7622_pwm_ch3_0_pins[] = { 53, };
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static int mt7622_pwm_ch3_0_funcs[] = { 3, };
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|
static int mt7622_pwm_ch3_1_pins[] = { 75, };
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|
static int mt7622_pwm_ch3_1_funcs[] = { 4, };
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static int mt7622_pwm_ch3_2_pins[] = { 97, };
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|
static int mt7622_pwm_ch3_2_funcs[] = { 0, };
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|
static int mt7622_pwm_ch4_0_pins[] = { 54, };
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|
static int mt7622_pwm_ch4_0_funcs[] = { 3, };
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|
static int mt7622_pwm_ch4_1_pins[] = { 67, };
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|
static int mt7622_pwm_ch4_1_funcs[] = { 3, };
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|
static int mt7622_pwm_ch4_2_pins[] = { 76, };
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static int mt7622_pwm_ch4_2_funcs[] = { 4, };
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static int mt7622_pwm_ch4_3_pins[] = { 98, };
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|
static int mt7622_pwm_ch4_3_funcs[] = { 0, };
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|
static int mt7622_pwm_ch5_0_pins[] = { 68, };
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|
static int mt7622_pwm_ch5_0_funcs[] = { 3, };
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|
static int mt7622_pwm_ch5_1_pins[] = { 77, };
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|
static int mt7622_pwm_ch5_1_funcs[] = { 4, };
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|
static int mt7622_pwm_ch5_2_pins[] = { 99, };
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|
static int mt7622_pwm_ch5_2_funcs[] = { 0, };
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|
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|
static int mt7622_pwm_ch6_0_pins[] = { 69, };
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|
static int mt7622_pwm_ch6_0_funcs[] = { 3, };
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|
|
|
static int mt7622_pwm_ch6_1_pins[] = { 78, };
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|
|
|
static int mt7622_pwm_ch6_1_funcs[] = { 4, };
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|
static int mt7622_pwm_ch6_2_pins[] = { 81, };
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|
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|
static int mt7622_pwm_ch6_2_funcs[] = { 4, };
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|
static int mt7622_pwm_ch6_3_pins[] = { 100, };
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|
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|
static int mt7622_pwm_ch6_3_funcs[] = { 0, };
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|
|
|
static int mt7622_pwm_ch7_0_pins[] = { 70, };
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|
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|
static int mt7622_pwm_ch7_0_funcs[] = { 3, };
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|
|
|
static int mt7622_pwm_ch7_1_pins[] = { 82, };
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|
|
|
static int mt7622_pwm_ch7_1_funcs[] = { 4, };
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|
|
static int mt7622_pwm_ch7_2_pins[] = { 101, };
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|
|
|
static int mt7622_pwm_ch7_2_funcs[] = { 0, };
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|
|
|
|
|
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|
|
/* SD */
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|
|
|
|
static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
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|
|
static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
|
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|
|
static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
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|
|
static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
|
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|
|
|
|
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|
|
/* Serial NAND */
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|
|
|
|
static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
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|
|
static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
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|
|
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|
|
/* SPI NOR */
|
|
|
|
|
static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
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|
|
|
static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
|
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|
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|
|
|
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|
|
/* SPIC */
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|
|
|
|
static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
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|
|
|
static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
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|
|
static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
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|
|
|
static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
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|
|
|
static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
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|
|
|
static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
|
|
|
|
|
static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
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|
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|
|
static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
|
|
|
|
|
static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
|
|
|
|
|
static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
|
|
|
|
|
static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
|
|
|
|
|
static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
|
|
|
|
|
|
|
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|
|
/* TDM */
|
|
|
|
|
static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
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|
|
|
|
static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
|
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|
|
|
static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
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|
|
|
static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
|
|
|
|
|
static int mt7622_tdm_0_out_data_pins[] = { 20, };
|
|
|
|
|
static int mt7622_tdm_0_out_data_funcs[] = { 3, };
|
|
|
|
|
static int mt7622_tdm_0_in_data_pins[] = { 21, };
|
|
|
|
|
static int mt7622_tdm_0_in_data_funcs[] = { 3, };
|
|
|
|
|
static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
|
|
|
|
|
static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
|
|
|
|
|
static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
|
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|
|
|
static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
|
|
|
|
|
static int mt7622_tdm_1_out_data_pins[] = { 55, };
|
|
|
|
|
static int mt7622_tdm_1_out_data_funcs[] = { 3, };
|
|
|
|
|
static int mt7622_tdm_1_in_data_pins[] = { 56, };
|
|
|
|
|
static int mt7622_tdm_1_in_data_funcs[] = { 3, };
|
|
|
|
|
|
|
|
|
|
/* UART */
|
|
|
|
|
static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
|
|
|
|
|
static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
|
|
|
|
|
static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
|
|
|
|
|
static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
|
|
|
|
|
static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
|
|
|
|
|
static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
|
|
|
|
|
static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
|
|
|
|
|
static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
|
|
|
|
|
static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
|
|
|
|
|
static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
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|
|
static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
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|
|
static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
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|
|
static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
|
|
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|
|
static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
|
|
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|
|
static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
|
|
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|
|
static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
|
|
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|
|
static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
|
|
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|
|
static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
|
|
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|
|
static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
|
|
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|
|
static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
|
|
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|
|
static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
|
|
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|
|
static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
|
|
|
|
|
static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
|
|
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|
|
static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
|
|
|
|
|
static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
|
|
|
|
|
static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
|
|
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|
|
static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
|
|
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|
|
static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
|
|
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|
|
static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
|
|
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|
|
static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
|
|
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|
|
static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
|
|
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|
|
static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
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|
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|
|
static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
|
|
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|
|
static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
|
|
|
|
|
static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
|
|
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|
|
static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
|
|
|
|
|
static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
|
|
|
|
|
static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
|
|
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|
|
static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
|
|
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|
|
static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
|
|
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|
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|
|
/* Watchdog */
|
|
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|
|
static int mt7622_watchdog_pins[] = { 78, };
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|
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|
|
static int mt7622_watchdog_funcs[] = { 0, };
|
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|
|
/* WLAN LED */
|
|
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|
|
static int mt7622_wled_pins[] = { 85, };
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|
|
static int mt7622_wled_funcs[] = { 0, };
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|
|
static const struct mtk_group_desc mt7622_groups[] = {
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|
|
PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
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|
PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
|
|
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|
|
PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
|
|
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|
|
PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
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|
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|
|
PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
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|
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|
|
PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
|
|
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|
|
PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
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|
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|
|
PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
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|
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|
|
PINCTRL_PIN_GROUP("esw", mt7622_esw),
|
|
|
|
|
PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
|
|
|
|
|
PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
|
|
|
|
|
PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
|
|
|
|
|
PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
|
|
|
|
|
PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
|
|
|
|
|
PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
|
|
|
|
|
PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
|
|
|
|
|
PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
|
|
|
|
|
PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
|
|
|
|
|
PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
|
|
|
|
|
PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
|
|
|
|
|
mt7622_tdm_0_out_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
|
|
|
|
|
mt7622_tdm_0_in_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
|
|
|
|
|
mt7622_tdm_1_out_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
|
|
|
|
|
mt7622_tdm_1_in_mclk_bclk_ws),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
|
|
|
|
|
PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
|
|
|
|
|
PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
|
|
|
|
|
PINCTRL_PIN_GROUP("wled", mt7622_wled),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Joint those groups owning the same capability in user point of view which
|
|
|
|
|
* allows that people tend to use through the device tree.
|
|
|
|
|
*/
|
|
|
|
|
static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
|
|
|
|
|
static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
|
|
|
|
|
"esw_p2_p3_p4", "mdc_mdio",
|
|
|
|
|
"rgmii_via_gmac1",
|
|
|
|
|
"rgmii_via_gmac2",
|
|
|
|
|
"rgmii_via_esw", };
|
|
|
|
|
static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
|
|
|
|
|
"i2c1_2", "i2c2_0", "i2c2_1",
|
|
|
|
|
"i2c2_2", };
|
|
|
|
|
static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
|
|
|
|
|
"i2s_in_mclk_bclk_ws",
|
|
|
|
|
"i2s1_in_data", "i2s2_in_data",
|
|
|
|
|
"i2s3_in_data", "i2s4_in_data",
|
|
|
|
|
"i2s1_out_data", "i2s2_out_data",
|
|
|
|
|
"i2s3_out_data", "i2s4_out_data", };
|
|
|
|
|
static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
|
|
|
|
|
"ir_0_rx", "ir_1_rx", "ir_2_rx"};
|
|
|
|
|
static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
|
|
|
|
|
"ephy1_led", "ephy2_led",
|
|
|
|
|
"ephy3_led", "ephy4_led",
|
|
|
|
|
"wled", };
|
|
|
|
|
static const char *const mt7622_flash_groups[] = { "par_nand", "snfi",
|
|
|
|
|
"spi_nor"};
|
|
|
|
|
static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken",
|
|
|
|
|
"pcie0_0_clkreq", "pcie0_1_waken",
|
|
|
|
|
"pcie0_1_clkreq", "pcie1_0_waken",
|
|
|
|
|
"pcie1_0_clkreq", "pcie0_pad_perst",
|
|
|
|
|
"pcie1_pad_perst", };
|
|
|
|
|
static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", };
|
|
|
|
|
static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
|
|
|
|
|
"pwm_ch1_2", "pwm_ch2_0",
|
|
|
|
|
"pwm_ch2_1", "pwm_ch2_2",
|
|
|
|
|
"pwm_ch3_0", "pwm_ch3_1",
|
|
|
|
|
"pwm_ch3_2", "pwm_ch4_0",
|
|
|
|
|
"pwm_ch4_1", "pwm_ch4_2",
|
|
|
|
|
"pwm_ch4_3", "pwm_ch5_0",
|
|
|
|
|
"pwm_ch5_1", "pwm_ch5_2",
|
|
|
|
|
"pwm_ch6_0", "pwm_ch6_1",
|
|
|
|
|
"pwm_ch6_2", "pwm_ch6_3",
|
|
|
|
|
"pwm_ch7_0", "pwm_ch7_1",
|
|
|
|
|
"pwm_ch7_2", };
|
|
|
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static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", };
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static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1",
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"spic1_0", "spic1_1", "spic2_0",
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"spic2_0_wp_hold", };
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static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
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"tdm_0_in_mclk_bclk_ws",
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"tdm_0_out_data",
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"tdm_0_in_data",
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"tdm_1_out_mclk_bclk_ws",
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"tdm_1_in_mclk_bclk_ws",
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"tdm_1_out_data",
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"tdm_1_in_data", };
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static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx",
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"uart1_0_tx_rx", "uart1_0_rts_cts",
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"uart1_1_tx_rx", "uart1_1_rts_cts",
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"uart2_0_tx_rx", "uart2_0_rts_cts",
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"uart2_1_tx_rx", "uart2_1_rts_cts",
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"uart2_2_tx_rx", "uart2_2_rts_cts",
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"uart2_3_tx_rx",
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"uart3_0_tx_rx",
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"uart3_1_tx_rx", "uart3_1_rts_cts",
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"uart4_0_tx_rx",
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"uart4_1_tx_rx", "uart4_1_rts_cts",
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"uart4_2_tx_rx",
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"uart4_2_rts_cts",};
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static const char *const mt7622_wdt_groups[] = { "watchdog", };
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static const struct mtk_function_desc mt7622_functions[] = {
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{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
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{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
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{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
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{"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
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{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
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{"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
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{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
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{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
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{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
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{"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
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{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
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{"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
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{"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
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{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
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{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
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};
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static struct mtk_pinctrl_soc mt7622_data = {
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.name = "mt7622_pinctrl",
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.reg_cal = mt7622_reg_cals,
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.pins = mt7622_pins,
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.npins = ARRAY_SIZE(mt7622_pins),
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.grps = mt7622_groups,
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.ngrps = ARRAY_SIZE(mt7622_groups),
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.funcs = mt7622_functions,
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.nfuncs = ARRAY_SIZE(mt7622_functions),
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2020-01-10 08:30:28 +00:00
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.gpio_mode = 1,
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.rev = MTK_PINCTRL_V0,
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2020-01-10 08:30:27 +00:00
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};
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static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
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{
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return mtk_pinctrl_common_probe(dev, &mt7622_data);
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}
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static const struct udevice_id mt7622_pctrl_match[] = {
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{ .compatible = "mediatek,mt7622-pinctrl" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mt7622_pinctrl) = {
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.name = "mt7622_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = mt7622_pctrl_match,
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.ops = &mtk_pinctrl_ops,
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.probe = mtk_pinctrl_mt7622_probe,
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2020-12-03 23:55:17 +00:00
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.priv_auto = sizeof(struct mtk_pinctrl_priv),
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2020-01-10 08:30:27 +00:00
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};
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