2018-07-04 12:01:23 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Xilinx
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*
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* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
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*/
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#include <common.h>
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2019-11-14 19:57:39 +00:00
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#include <cpu_func.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2018-07-04 12:01:23 +00:00
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#include <asm/arch/sys_proto.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2018-07-04 12:01:23 +00:00
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <spi.h>
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2021-01-20 16:39:46 +00:00
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#include <spi-mem.h>
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2018-07-04 12:01:23 +00:00
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#include <ubi_uboot.h>
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#include <wait_bit.h>
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2020-02-03 14:36:16 +00:00
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#include <dm/device_compat.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-02-03 14:36:15 +00:00
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#include <linux/err.h>
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2022-08-25 12:59:04 +00:00
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#include <linux/sizes.h>
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2022-08-25 12:59:01 +00:00
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#include <zynqmp_firmware.h>
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2018-07-04 12:01:23 +00:00
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#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
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#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
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#define GQSPI_CONFIG_DMA_MODE (2 << 30)
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#define GQSPI_CONFIG_CPHA_MASK BIT(2)
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#define GQSPI_CONFIG_CPOL_MASK BIT(1)
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/*
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* QSPI Interrupt Registers bit Masks
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*
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* All the four interrupt registers (Status/Mask/Enable/Disable) have the same
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* bit definitions.
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*/
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#define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
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#define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
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2021-10-19 14:13:00 +00:00
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#define GQSPI_IXR_TXFIFOEMPTY_MASK 0x00000100 /* QSPI TX FIFO is Empty */
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2018-07-04 12:01:23 +00:00
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#define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
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#define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
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2021-05-25 12:36:27 +00:00
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#define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */
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2018-07-04 12:01:23 +00:00
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#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
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GQSPI_IXR_RXNEMTY_MASK)
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/*
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* QSPI Enable Register bit Masks
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*
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* This register is used to enable or disable the QSPI controller
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*/
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#define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
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#define GQSPI_GFIFO_LOW_BUS BIT(14)
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#define GQSPI_GFIFO_CS_LOWER BIT(12)
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#define GQSPI_GFIFO_UP_BUS BIT(15)
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#define GQSPI_GFIFO_CS_UPPER BIT(13)
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#define GQSPI_SPI_MODE_QSPI (3 << 10)
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#define GQSPI_SPI_MODE_SPI BIT(10)
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#define GQSPI_SPI_MODE_DUAL_SPI (2 << 10)
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#define GQSPI_IMD_DATA_CS_ASSERT 5
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#define GQSPI_IMD_DATA_CS_DEASSERT 5
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#define GQSPI_GFIFO_TX BIT(16)
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#define GQSPI_GFIFO_RX BIT(17)
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#define GQSPI_GFIFO_STRIPE_MASK BIT(18)
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#define GQSPI_GFIFO_IMD_MASK 0xFF
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#define GQSPI_GFIFO_EXP_MASK BIT(9)
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#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8)
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#define GQSPI_STRT_GEN_FIFO BIT(28)
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#define GQSPI_GEN_FIFO_STRT_MOD BIT(29)
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#define GQSPI_GFIFO_WP_HOLD BIT(19)
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#define GQSPI_BAUD_DIV_MASK (7 << 3)
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#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3)
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#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE
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#define GQSPI_DMA_DST_I_STS_DONE BIT(1)
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#define GQSPI_DMA_DST_I_STS_MASK 0xFE
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#define MODEBITS 0x6
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#define GQSPI_GFIFO_SELECT BIT(0)
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#define GQSPI_FIFO_THRESHOLD 1
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2021-08-20 13:43:17 +00:00
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#define GQSPI_GENFIFO_THRESHOLD 31
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2018-07-04 12:01:23 +00:00
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#define SPI_XFER_ON_BOTH 0
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#define SPI_XFER_ON_LOWER 1
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#define SPI_XFER_ON_UPPER 2
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#define GQSPI_DMA_ALIGN 0x4
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#define GQSPI_MAX_BAUD_RATE_VAL 7
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#define GQSPI_DFLT_BAUD_RATE_VAL 2
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#define GQSPI_TIMEOUT 100000000
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#define GQSPI_BAUD_DIV_SHIFT 2
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#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5
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2022-11-23 09:04:51 +00:00
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#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1
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2018-07-04 12:01:23 +00:00
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#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3
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#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3
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#define GQSPI_USE_DATA_DLY 0x1
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#define GQSPI_USE_DATA_DLY_SHIFT 31
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#define GQSPI_DATA_DLY_ADJ_VALUE 0x2
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#define GQSPI_DATA_DLY_ADJ_SHIFT 28
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#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
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#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
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#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
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2022-11-16 15:40:30 +00:00
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#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
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IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
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2022-08-25 12:59:01 +00:00
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0xFF180390 : 0xF103003C
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2018-07-04 12:01:23 +00:00
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#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
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2022-08-25 12:59:01 +00:00
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#define GQSPI_FREQ_37_5MHZ 37500000
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2018-07-04 12:01:23 +00:00
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#define GQSPI_FREQ_40MHZ 40000000
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#define GQSPI_FREQ_100MHZ 100000000
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#define GQSPI_FREQ_150MHZ 150000000
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#define IOU_TAPDLY_BYPASS_MASK 0x7
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#define GQSPI_REG_OFFSET 0x100
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#define GQSPI_DMA_REG_OFFSET 0x800
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/* QSPI register offsets */
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struct zynqmp_qspi_regs {
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u32 confr; /* 0x00 */
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u32 isr; /* 0x04 */
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u32 ier; /* 0x08 */
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u32 idisr; /* 0x0C */
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u32 imaskr; /* 0x10 */
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u32 enbr; /* 0x14 */
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u32 dr; /* 0x18 */
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u32 txd0r; /* 0x1C */
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u32 drxr; /* 0x20 */
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u32 sicr; /* 0x24 */
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u32 txftr; /* 0x28 */
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u32 rxftr; /* 0x2C */
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u32 gpior; /* 0x30 */
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u32 reserved0; /* 0x34 */
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u32 lpbkdly; /* 0x38 */
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u32 reserved1; /* 0x3C */
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u32 genfifo; /* 0x40 */
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u32 gqspisel; /* 0x44 */
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u32 reserved2; /* 0x48 */
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u32 gqfifoctrl; /* 0x4C */
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u32 gqfthr; /* 0x50 */
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u32 gqpollcfg; /* 0x54 */
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u32 gqpollto; /* 0x58 */
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u32 gqxfersts; /* 0x5C */
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u32 gqfifosnap; /* 0x60 */
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u32 gqrxcpy; /* 0x64 */
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u32 reserved3[36]; /* 0x68 */
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u32 gqspidlyadj; /* 0xF8 */
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};
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struct zynqmp_qspi_dma_regs {
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u32 dmadst; /* 0x00 */
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u32 dmasize; /* 0x04 */
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u32 dmasts; /* 0x08 */
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u32 dmactrl; /* 0x0C */
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u32 reserved0; /* 0x10 */
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u32 dmaisr; /* 0x14 */
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u32 dmaier; /* 0x18 */
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u32 dmaidr; /* 0x1C */
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u32 dmaimr; /* 0x20 */
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u32 dmactrl2; /* 0x24 */
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u32 dmadstmsb; /* 0x28 */
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};
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2020-12-03 23:55:23 +00:00
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struct zynqmp_qspi_plat {
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2018-07-04 12:01:23 +00:00
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struct zynqmp_qspi_regs *regs;
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struct zynqmp_qspi_dma_regs *dma_regs;
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u32 frequency;
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u32 speed_hz;
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2022-08-25 12:59:03 +00:00
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unsigned int io_mode;
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2018-07-04 12:01:23 +00:00
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};
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struct zynqmp_qspi_priv {
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struct zynqmp_qspi_regs *regs;
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struct zynqmp_qspi_dma_regs *dma_regs;
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const void *tx_buf;
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void *rx_buf;
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unsigned int len;
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2022-08-25 12:59:03 +00:00
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unsigned int io_mode;
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2018-07-04 12:01:23 +00:00
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int bytes_to_transfer;
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int bytes_to_receive;
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2021-01-20 16:39:46 +00:00
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const struct spi_mem_op *op;
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2018-07-04 12:01:23 +00:00
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};
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2023-03-01 10:33:33 +00:00
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__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
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{
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return 0;
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}
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2020-12-03 23:55:21 +00:00
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static int zynqmp_qspi_of_to_plat(struct udevice *bus)
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2018-07-04 12:01:23 +00:00
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{
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2020-12-23 02:30:28 +00:00
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struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
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2018-07-04 12:01:23 +00:00
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debug("%s\n", __func__);
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2020-07-17 05:36:48 +00:00
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plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
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2018-07-04 12:01:23 +00:00
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GQSPI_REG_OFFSET);
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plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
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2020-07-17 05:36:48 +00:00
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(dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
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2018-07-04 12:01:23 +00:00
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2022-08-25 12:59:03 +00:00
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plat->io_mode = dev_read_bool(bus, "has-io-mode");
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2018-07-04 12:01:23 +00:00
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return 0;
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}
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static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
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{
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u32 config_reg;
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struct zynqmp_qspi_regs *regs = priv->regs;
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writel(GQSPI_GFIFO_SELECT, ®s->gqspisel);
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writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
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writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
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writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
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2021-08-20 13:43:17 +00:00
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writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr);
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2018-07-04 12:01:23 +00:00
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writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
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2021-08-20 13:43:17 +00:00
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writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
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2018-07-04 12:01:23 +00:00
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config_reg = readl(®s->confr);
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config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
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GQSPI_CONFIG_MODE_EN_MASK);
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2022-08-25 12:59:03 +00:00
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config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
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config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
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if (!priv->io_mode)
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config_reg |= GQSPI_CONFIG_DMA_MODE;
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2018-07-04 12:01:23 +00:00
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writel(config_reg, ®s->confr);
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writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
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}
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static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
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{
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u32 gqspi_fifo_reg = 0;
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gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
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GQSPI_GFIFO_CS_LOWER;
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return gqspi_fifo_reg;
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}
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2021-01-20 16:39:46 +00:00
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static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
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{
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switch (buswidth) {
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case 1:
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return GQSPI_SPI_MODE_SPI;
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case 2:
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return GQSPI_SPI_MODE_DUAL_SPI;
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case 4:
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return GQSPI_SPI_MODE_QSPI;
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default:
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debug("Unsupported bus width %u\n", buswidth);
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return GQSPI_SPI_MODE_SPI;
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}
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}
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2018-07-04 12:01:23 +00:00
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static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
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u32 gqspi_fifo_reg)
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{
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struct zynqmp_qspi_regs *regs = priv->regs;
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2021-05-25 12:36:27 +00:00
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u32 config_reg, ier;
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2018-07-04 12:01:23 +00:00
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int ret = 0;
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2021-08-20 13:43:16 +00:00
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writel(gqspi_fifo_reg, ®s->genfifo);
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2021-05-25 12:36:27 +00:00
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config_reg = readl(®s->confr);
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/* Manual start if needed */
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config_reg |= GQSPI_STRT_GEN_FIFO;
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writel(config_reg, ®s->confr);
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/* Enable interrupts */
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ier = readl(®s->ier);
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2021-08-20 13:43:16 +00:00
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ier |= GQSPI_IXR_GFEMTY_MASK;
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2021-05-25 12:36:27 +00:00
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writel(ier, ®s->ier);
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2021-08-20 13:43:16 +00:00
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/* Wait until the gen fifo is empty to write the new command */
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ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
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2018-07-04 12:01:23 +00:00
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GQSPI_TIMEOUT, 1);
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if (ret)
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printf("%s Timeout\n", __func__);
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}
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static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
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{
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u32 gqspi_fifo_reg = 0;
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|
|
|
|
|
|
|
if (is_on) {
|
|
|
|
gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
|
|
|
|
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
|
|
|
|
GQSPI_IMD_DATA_CS_ASSERT;
|
|
|
|
} else {
|
|
|
|
gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
|
|
|
|
gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
|
|
|
|
}
|
|
|
|
|
|
|
|
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
|
|
|
|
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
|
|
|
|
}
|
|
|
|
|
2022-10-04 05:37:30 +00:00
|
|
|
static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
|
2018-07-04 12:01:23 +00:00
|
|
|
{
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
|
2018-07-04 12:01:23 +00:00
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
|
|
|
|
u32 reqhz = 0;
|
|
|
|
|
|
|
|
clk_rate = plat->frequency;
|
|
|
|
reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
|
|
|
|
|
|
|
|
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
|
|
|
|
__func__, reqhz, clk_rate, baudrateval);
|
|
|
|
|
2022-09-19 12:21:04 +00:00
|
|
|
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
|
|
|
|
IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
|
2022-08-25 12:59:01 +00:00
|
|
|
if (reqhz <= GQSPI_FREQ_40MHZ) {
|
|
|
|
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
|
|
|
|
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
|
|
|
|
} else if (reqhz <= GQSPI_FREQ_100MHZ) {
|
|
|
|
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
|
|
|
|
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
|
|
|
|
lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
|
|
|
|
datadlyadj = (GQSPI_USE_DATA_DLY <<
|
|
|
|
GQSPI_USE_DATA_DLY_SHIFT) |
|
|
|
|
(GQSPI_DATA_DLY_ADJ_VALUE <<
|
|
|
|
GQSPI_DATA_DLY_ADJ_SHIFT);
|
|
|
|
} else if (reqhz <= GQSPI_FREQ_150MHZ) {
|
|
|
|
lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
|
|
|
|
GQSPI_LPBK_DLY_ADJ_DLY_0;
|
|
|
|
}
|
|
|
|
zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
|
|
|
|
IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
|
|
|
|
} else {
|
|
|
|
if (reqhz <= GQSPI_FREQ_37_5MHZ) {
|
|
|
|
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
|
|
|
|
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
|
|
|
|
} else if (reqhz <= GQSPI_FREQ_100MHZ) {
|
|
|
|
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
|
|
|
|
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
|
|
|
|
lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
|
|
|
|
datadlyadj = GQSPI_USE_DATA_DLY <<
|
|
|
|
GQSPI_USE_DATA_DLY_SHIFT;
|
|
|
|
} else if (reqhz <= GQSPI_FREQ_150MHZ) {
|
|
|
|
lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
|
|
|
|
(GQSPI_LPBK_DLY_ADJ_DLY_1 <<
|
|
|
|
GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
|
|
|
|
}
|
|
|
|
writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
|
2018-07-04 12:01:23 +00:00
|
|
|
}
|
|
|
|
writel(lpbkdlyadj, ®s->lpbkdly);
|
|
|
|
writel(datadlyadj, ®s->gqspidlyadj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
|
|
|
|
{
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
|
2018-07-04 12:01:23 +00:00
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
u32 confr;
|
|
|
|
u8 baud_rate_val = 0;
|
|
|
|
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
if (speed > plat->frequency)
|
|
|
|
speed = plat->frequency;
|
|
|
|
|
2021-01-20 20:28:30 +00:00
|
|
|
if (plat->speed_hz != speed) {
|
|
|
|
/* Set the clock frequency */
|
|
|
|
/* If speed == 0, default to lowest speed */
|
2018-07-04 12:01:23 +00:00
|
|
|
while ((baud_rate_val < 8) &&
|
|
|
|
((plat->frequency /
|
|
|
|
(2 << baud_rate_val)) > speed))
|
|
|
|
baud_rate_val++;
|
|
|
|
|
|
|
|
if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
|
|
|
|
baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
|
|
|
|
|
|
|
|
plat->speed_hz = plat->frequency / (2 << baud_rate_val);
|
|
|
|
|
2021-01-20 20:28:30 +00:00
|
|
|
confr = readl(®s->confr);
|
|
|
|
confr &= ~GQSPI_BAUD_DIV_MASK;
|
|
|
|
confr |= (baud_rate_val << 3);
|
|
|
|
writel(confr, ®s->confr);
|
|
|
|
zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
|
|
|
|
|
|
|
|
debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
|
|
|
|
}
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_probe(struct udevice *bus)
|
|
|
|
{
|
2020-12-03 23:55:23 +00:00
|
|
|
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
|
2018-07-04 12:01:23 +00:00
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct clk clk;
|
|
|
|
unsigned long clock;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
|
|
|
|
|
|
|
|
priv->regs = plat->regs;
|
|
|
|
priv->dma_regs = plat->dma_regs;
|
2022-08-25 12:59:03 +00:00
|
|
|
priv->io_mode = plat->io_mode;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
ret = clk_get_by_index(bus, 0, &clk);
|
|
|
|
if (ret < 0) {
|
2020-09-15 14:45:12 +00:00
|
|
|
dev_err(bus, "failed to get clock\n");
|
2018-07-04 12:01:23 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
clock = clk_get_rate(&clk);
|
|
|
|
if (IS_ERR_VALUE(clock)) {
|
2020-09-15 14:45:12 +00:00
|
|
|
dev_err(bus, "failed to get rate\n");
|
2018-07-04 12:01:23 +00:00
|
|
|
return clock;
|
|
|
|
}
|
|
|
|
debug("%s: CLK %ld\n", __func__, clock);
|
|
|
|
|
|
|
|
ret = clk_enable(&clk);
|
2021-02-09 14:28:15 +00:00
|
|
|
if (ret) {
|
2020-09-15 14:45:12 +00:00
|
|
|
dev_err(bus, "failed to enable clock\n");
|
2018-07-04 12:01:23 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
plat->frequency = clock;
|
|
|
|
plat->speed_hz = plat->frequency / 2;
|
|
|
|
|
|
|
|
/* init the zynq spi hw */
|
|
|
|
zynqmp_qspi_init_hw(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
|
|
|
|
{
|
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
u32 confr;
|
|
|
|
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
/* Set the SPI Clock phase and polarities */
|
|
|
|
confr = readl(®s->confr);
|
2022-08-25 12:59:05 +00:00
|
|
|
confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
if (mode & SPI_CPHA)
|
|
|
|
confr |= GQSPI_CONFIG_CPHA_MASK;
|
|
|
|
if (mode & SPI_CPOL)
|
|
|
|
confr |= GQSPI_CONFIG_CPOL_MASK;
|
|
|
|
|
|
|
|
writel(confr, ®s->confr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
|
|
|
|
{
|
|
|
|
u32 data;
|
|
|
|
int ret = 0;
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
u32 *buf = (u32 *)priv->tx_buf;
|
|
|
|
u32 len = size;
|
|
|
|
|
|
|
|
debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
|
|
|
|
size);
|
|
|
|
|
|
|
|
while (size) {
|
|
|
|
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
|
|
|
|
GQSPI_TIMEOUT, 1);
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Timeout\n", __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size >= 4) {
|
|
|
|
writel(*buf, ®s->txd0r);
|
|
|
|
buf++;
|
|
|
|
size -= 4;
|
|
|
|
} else {
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
data = *((u8 *)buf);
|
|
|
|
buf += 1;
|
|
|
|
data |= GENMASK(31, 8);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
data = *((u16 *)buf);
|
|
|
|
buf += 2;
|
|
|
|
data |= GENMASK(31, 16);
|
|
|
|
break;
|
|
|
|
case 3:
|
2020-11-19 12:00:36 +00:00
|
|
|
data = *buf;
|
|
|
|
buf += 3;
|
2018-07-04 12:01:23 +00:00
|
|
|
data |= GENMASK(31, 24);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
writel(data, ®s->txd0r);
|
|
|
|
size = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-19 14:13:00 +00:00
|
|
|
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
|
|
|
|
GQSPI_TIMEOUT, 1);
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Timeout\n", __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-07-04 12:01:23 +00:00
|
|
|
priv->tx_buf += len;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
|
|
|
|
{
|
2021-01-20 16:39:46 +00:00
|
|
|
const struct spi_mem_op *op = priv->op;
|
2018-07-04 12:01:23 +00:00
|
|
|
u32 gen_fifo_cmd;
|
2021-01-20 16:39:46 +00:00
|
|
|
u8 i, dummy_cycles, addr;
|
|
|
|
|
|
|
|
/* Send opcode */
|
|
|
|
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
|
|
|
|
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
|
|
|
|
gen_fifo_cmd |= GQSPI_GFIFO_TX;
|
|
|
|
gen_fifo_cmd |= op->cmd.opcode;
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
|
|
|
|
/* Send address */
|
|
|
|
for (i = 0; i < op->addr.nbytes; i++) {
|
|
|
|
addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
|
2021-01-20 16:39:46 +00:00
|
|
|
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
|
|
|
|
gen_fifo_cmd |= GQSPI_GFIFO_TX;
|
|
|
|
gen_fifo_cmd |= addr;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
|
|
|
|
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
}
|
2021-01-20 16:39:46 +00:00
|
|
|
|
|
|
|
/* Send dummy */
|
|
|
|
if (op->dummy.nbytes) {
|
|
|
|
dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
|
|
|
|
|
|
|
|
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
|
|
|
|
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
|
|
|
|
gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
|
|
|
|
gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
|
|
|
|
gen_fifo_cmd |= dummy_cycles;
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
}
|
2018-07-04 12:01:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
|
|
|
|
u32 *gen_fifo_cmd)
|
|
|
|
{
|
|
|
|
u32 expval = 8;
|
|
|
|
u32 len;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
if (priv->len > 255) {
|
|
|
|
if (priv->len & (1 << expval)) {
|
|
|
|
*gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
|
|
|
|
*gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
|
|
|
|
*gen_fifo_cmd |= expval;
|
|
|
|
priv->len -= (1 << expval);
|
|
|
|
return expval;
|
|
|
|
}
|
|
|
|
expval++;
|
|
|
|
} else {
|
|
|
|
*gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
|
|
|
|
GQSPI_GFIFO_EXP_MASK);
|
|
|
|
*gen_fifo_cmd |= (u8)priv->len;
|
|
|
|
len = (u8)priv->len;
|
|
|
|
priv->len = 0;
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
|
|
|
|
{
|
|
|
|
u32 gen_fifo_cmd;
|
|
|
|
u32 len;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
|
2021-01-20 16:39:46 +00:00
|
|
|
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
|
2022-08-25 12:59:05 +00:00
|
|
|
gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
while (priv->len) {
|
|
|
|
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
|
|
|
|
debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
|
|
|
|
|
|
|
|
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
|
2022-08-25 12:59:05 +00:00
|
|
|
ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
|
2018-07-04 12:01:23 +00:00
|
|
|
else
|
2022-08-25 12:59:05 +00:00
|
|
|
ret = zynqmp_qspi_fill_tx_fifo(priv, len);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-08-25 12:59:03 +00:00
|
|
|
static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
|
|
|
|
u32 gen_fifo_cmd, u32 *buf)
|
|
|
|
{
|
|
|
|
u32 len;
|
|
|
|
u32 actuallen = priv->len;
|
|
|
|
u32 config_reg, ier, isr;
|
|
|
|
u32 timeout = GQSPI_TIMEOUT;
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
u32 last_bits;
|
|
|
|
u32 *traverse = buf;
|
|
|
|
|
|
|
|
while (priv->len) {
|
|
|
|
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
|
|
|
|
/* If exponent bit is set, reset immediate to be 2^len */
|
|
|
|
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
|
|
|
|
priv->bytes_to_receive = (1 << len);
|
|
|
|
else
|
|
|
|
priv->bytes_to_receive = len;
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
|
|
|
|
/* Manual start */
|
|
|
|
config_reg = readl(®s->confr);
|
|
|
|
config_reg |= GQSPI_STRT_GEN_FIFO;
|
|
|
|
writel(config_reg, ®s->confr);
|
|
|
|
/* Enable RX interrupts for IO mode */
|
|
|
|
ier = readl(®s->ier);
|
|
|
|
ier |= GQSPI_IXR_ALL_MASK;
|
|
|
|
writel(ier, ®s->ier);
|
|
|
|
while (priv->bytes_to_receive && timeout) {
|
|
|
|
isr = readl(®s->isr);
|
|
|
|
if (isr & GQSPI_IXR_RXNEMTY_MASK) {
|
|
|
|
if (priv->bytes_to_receive >= 4) {
|
|
|
|
*traverse = readl(®s->drxr);
|
|
|
|
traverse++;
|
|
|
|
priv->bytes_to_receive -= 4;
|
|
|
|
} else {
|
|
|
|
last_bits = readl(®s->drxr);
|
|
|
|
memcpy(traverse, &last_bits,
|
|
|
|
priv->bytes_to_receive);
|
|
|
|
priv->bytes_to_receive = 0;
|
|
|
|
}
|
|
|
|
timeout = GQSPI_TIMEOUT;
|
|
|
|
} else {
|
|
|
|
udelay(1);
|
|
|
|
timeout--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
|
|
|
|
(unsigned long)buf, (unsigned long)priv->rx_buf,
|
|
|
|
*buf, actuallen);
|
|
|
|
if (!timeout) {
|
|
|
|
printf("IO timeout: %d\n", readl(®s->isr));
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-07-04 12:01:23 +00:00
|
|
|
static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
|
|
|
|
u32 gen_fifo_cmd, u32 *buf)
|
|
|
|
{
|
2022-11-25 10:44:13 +00:00
|
|
|
unsigned long addr;
|
2021-08-20 13:43:17 +00:00
|
|
|
u32 size;
|
2018-07-04 12:01:23 +00:00
|
|
|
u32 actuallen = priv->len;
|
2022-08-25 12:59:04 +00:00
|
|
|
u32 totallen = priv->len;
|
2018-07-04 12:01:23 +00:00
|
|
|
int ret = 0;
|
|
|
|
struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
|
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
while (totallen) {
|
|
|
|
if (totallen >= SZ_512M)
|
|
|
|
priv->len = SZ_256M;
|
|
|
|
else
|
|
|
|
priv->len = totallen;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
totallen -= priv->len; /* Save remaining bytes length to read */
|
|
|
|
actuallen = priv->len; /* Actual number of bytes reading */
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-11-25 10:44:13 +00:00
|
|
|
writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst);
|
|
|
|
writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0),
|
|
|
|
&dma_regs->dmadstmsb);
|
2022-08-25 12:59:04 +00:00
|
|
|
writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
|
|
|
|
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
|
|
|
|
addr = (unsigned long)buf;
|
|
|
|
size = roundup(priv->len, GQSPI_DMA_ALIGN);
|
2023-09-15 03:17:58 +00:00
|
|
|
invalidate_dcache_range(addr, addr + size);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
while (priv->len) {
|
|
|
|
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
|
|
|
|
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
|
|
|
|
|
|
|
|
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = wait_for_bit_le32(&dma_regs->dmaisr,
|
|
|
|
GQSPI_DMA_DST_I_STS_DONE, 1,
|
|
|
|
GQSPI_TIMEOUT, 1);
|
|
|
|
if (ret) {
|
|
|
|
printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
|
|
|
|
(unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
|
|
|
|
actuallen);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
if (buf != priv->rx_buf)
|
|
|
|
memcpy(priv->rx_buf, buf, actuallen);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2022-08-25 12:59:04 +00:00
|
|
|
buf = (u32 *)((u8 *)buf + actuallen);
|
|
|
|
priv->rx_buf = (u8 *)priv->rx_buf + actuallen;
|
|
|
|
}
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
|
|
|
|
{
|
|
|
|
u32 gen_fifo_cmd;
|
|
|
|
u32 *buf;
|
|
|
|
u32 actuallen = priv->len;
|
|
|
|
|
|
|
|
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
|
2021-01-20 16:39:46 +00:00
|
|
|
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
|
2022-08-25 12:59:05 +00:00
|
|
|
gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if receive buffer is aligned to 4 byte and length
|
|
|
|
* is multiples of four byte as we are using dma to receive.
|
|
|
|
*/
|
2022-08-25 12:59:03 +00:00
|
|
|
if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
|
|
|
|
!(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) {
|
2018-07-04 12:01:23 +00:00
|
|
|
buf = (u32 *)priv->rx_buf;
|
2022-08-25 12:59:03 +00:00
|
|
|
if (priv->io_mode)
|
|
|
|
return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf);
|
|
|
|
else
|
|
|
|
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
|
2018-07-04 12:01:23 +00:00
|
|
|
}
|
|
|
|
|
2022-08-25 12:59:05 +00:00
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, GQSPI_DMA_ALIGN));
|
2018-07-04 12:01:23 +00:00
|
|
|
buf = (u32 *)tmp;
|
|
|
|
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_claim_bus(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct udevice *bus = dev->parent;
|
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
|
|
|
|
writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynqmp_qspi_release_bus(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct udevice *bus = dev->parent;
|
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynqmp_qspi_regs *regs = priv->regs;
|
|
|
|
|
|
|
|
writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
static int zynqmp_qspi_exec_op(struct spi_slave *slave,
|
|
|
|
const struct spi_mem_op *op)
|
2018-07-04 12:01:23 +00:00
|
|
|
{
|
2021-01-20 16:39:46 +00:00
|
|
|
struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
|
|
|
|
int ret = 0;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
priv->op = op;
|
|
|
|
priv->tx_buf = op->data.buf.out;
|
|
|
|
priv->rx_buf = op->data.buf.in;
|
|
|
|
priv->len = op->data.nbytes;
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
zynqmp_qspi_chipselect(priv, 1);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
/* Send opcode, addr, dummy */
|
|
|
|
zynqmp_qspi_genfifo_cmd(priv);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
/* Request the transfer */
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
|
|
ret = zynqmp_qspi_genfifo_fill_rx(priv);
|
|
|
|
else if (op->data.dir == SPI_MEM_DATA_OUT)
|
|
|
|
ret = zynqmp_qspi_genfifo_fill_tx(priv);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
zynqmp_qspi_chipselect(priv, 0);
|
2018-07-04 12:01:23 +00:00
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
return ret;
|
2018-07-04 12:01:23 +00:00
|
|
|
}
|
|
|
|
|
2021-01-20 16:39:46 +00:00
|
|
|
static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
|
|
|
|
.exec_op = zynqmp_qspi_exec_op,
|
|
|
|
};
|
|
|
|
|
2018-07-04 12:01:23 +00:00
|
|
|
static const struct dm_spi_ops zynqmp_qspi_ops = {
|
|
|
|
.claim_bus = zynqmp_qspi_claim_bus,
|
|
|
|
.release_bus = zynqmp_qspi_release_bus,
|
|
|
|
.set_speed = zynqmp_qspi_set_speed,
|
|
|
|
.set_mode = zynqmp_qspi_set_mode,
|
2021-01-20 16:39:46 +00:00
|
|
|
.mem_ops = &zynqmp_qspi_mem_ops,
|
2018-07-04 12:01:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id zynqmp_qspi_ids[] = {
|
|
|
|
{ .compatible = "xlnx,zynqmp-qspi-1.0" },
|
2018-11-29 07:48:28 +00:00
|
|
|
{ .compatible = "xlnx,versal-qspi-1.0" },
|
2018-07-04 12:01:23 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(zynqmp_qspi) = {
|
|
|
|
.name = "zynqmp_qspi",
|
|
|
|
.id = UCLASS_SPI,
|
|
|
|
.of_match = zynqmp_qspi_ids,
|
|
|
|
.ops = &zynqmp_qspi_ops,
|
2020-12-03 23:55:21 +00:00
|
|
|
.of_to_plat = zynqmp_qspi_of_to_plat,
|
2020-12-03 23:55:23 +00:00
|
|
|
.plat_auto = sizeof(struct zynqmp_qspi_plat),
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct zynqmp_qspi_priv),
|
2018-07-04 12:01:23 +00:00
|
|
|
.probe = zynqmp_qspi_probe,
|
|
|
|
};
|