2007-08-17 00:23:50 +00:00
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/*
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*
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2012-03-26 21:49:06 +00:00
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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2007-08-17 00:23:50 +00:00
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2007-08-17 00:23:50 +00:00
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*/
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/* CPU specific interrupt routine */
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#include <common.h>
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#include <asm/immap.h>
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2012-03-26 21:49:06 +00:00
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#include <asm/io.h>
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2007-08-17 00:23:50 +00:00
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int interrupt_init(void)
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{
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2012-03-26 21:49:06 +00:00
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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2007-08-17 00:23:50 +00:00
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/* Make sure all interrupts are disabled */
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2012-03-26 21:49:06 +00:00
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setbits_be32(&intp->imrl0, 0x1);
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2007-08-17 00:23:50 +00:00
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enable_interrupts();
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return 0;
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}
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#if defined(CONFIG_MCFTMR)
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void dtimer_intr_setup(void)
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{
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2012-03-26 21:49:06 +00:00
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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2007-08-17 00:23:50 +00:00
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2012-03-26 21:49:06 +00:00
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out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
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clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
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clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
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2007-08-17 00:23:50 +00:00
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}
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#endif
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