2008-02-04 21:38:20 +00:00
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/*
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* MCF5274/5 Internal Memory Map
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*
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* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
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* Based on work Copyright (c) 2003 Josef Baumgartner
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* <josef.baumgartner@telex.de>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2008-02-04 21:38:20 +00:00
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*/
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#ifndef __IMMAP_5275__
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#define __IMMAP_5275__
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2008-10-16 13:01:15 +00:00
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#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
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#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
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#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
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#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
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#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
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#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
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#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
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#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
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#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
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#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
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#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
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#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
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#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
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#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
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#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
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#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
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#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
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#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
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#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
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#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
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#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
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#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
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#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
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#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
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#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
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#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
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#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
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2008-02-04 21:38:20 +00:00
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2008-10-21 10:03:07 +00:00
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/mdha.h>
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#include <asm/coldfire/pwm.h>
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#include <asm/coldfire/qspi.h>
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#include <asm/coldfire/rng.h>
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#include <asm/coldfire/skha.h>
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2008-02-04 21:38:20 +00:00
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/* System configuration registers
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*/
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typedef struct sys_ctrl {
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u32 ipsbar;
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u32 res1;
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u32 rambar;
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u32 res2;
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u8 crsr;
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u8 cwcr;
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u8 lpicr;
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u8 cwsr;
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u8 res3[8];
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u32 mpark;
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u8 mpr;
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u8 res4[3];
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u8 pacr0;
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u8 pacr1;
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u8 pacr2;
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u8 pacr3;
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u8 pacr4;
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u8 res5;
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u8 pacr5;
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u8 pacr6;
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u8 pacr7;
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u8 res6;
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u8 pacr8;
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u8 res7;
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u8 gpacr;
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u8 res8[3];
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} sysctrl_t;
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/* SDRAM controller registers, offset: 0x040
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*/
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typedef struct sdram_ctrl {
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u32 sdmr;
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u32 sdcr;
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u32 sdcfg1;
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u32 sdcfg2;
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u32 sdbar0;
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u32 sdbmr0;
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u32 sdbar1;
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u32 sdbmr1;
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} sdramctrl_t;
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/* DMA module registers, offset 0x100
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*/
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typedef struct dma_ctrl {
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u32 sar;
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u32 dar;
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u32 dsrbcr;
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u32 dcr;
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} dma_t;
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/* GPIO port registers
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*/
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typedef struct gpio_ctrl {
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/* Port Output Data Registers */
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u8 podr_res1[4];
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u8 podr_busctl;
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u8 podr_addr;
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u8 podr_res2[2];
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u8 podr_cs;
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u8 podr_res3;
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u8 podr_fec0h;
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u8 podr_fec0l;
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u8 podr_feci2c;
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u8 podr_qspi;
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u8 podr_sdram;
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u8 podr_timerh;
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u8 podr_timerl;
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u8 podr_uartl;
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u8 podr_fec1h;
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u8 podr_fec1l;
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u8 podr_bs;
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u8 podr_res4;
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u8 podr_usbh;
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u8 podr_usbl;
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u8 podr_uarth;
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u8 podr_res5[3];
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/* Port Data Direction Registers */
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u8 pddr_res1[4];
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u8 pddr_busctl;
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u8 pddr_addr;
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u8 pddr_res2[2];
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u8 pddr_cs;
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u8 pddr_res3;
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u8 pddr_fec0h;
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u8 pddr_fec0l;
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u8 pddr_feci2c;
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u8 pddr_qspi;
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u8 pddr_sdram;
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u8 pddr_timerh;
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u8 pddr_timerl;
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u8 pddr_uartl;
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u8 pddr_fec1h;
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u8 pddr_fec1l;
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u8 pddr_bs;
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u8 pddr_res4;
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u8 pddr_usbh;
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u8 pddr_usbl;
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u8 pddr_uarth;
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u8 pddr_res5[3];
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/* Port Pin Data/Set Registers */
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u8 ppdsdr_res1[4];
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u8 ppdsdr_busctl;
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u8 ppdsdr_addr;
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u8 ppdsdr_res2[2];
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u8 ppdsdr_cs;
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u8 ppdsdr_res3;
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u8 ppdsdr_fec0h;
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u8 ppdsdr_fec0l;
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u8 ppdsdr_feci2c;
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u8 ppdsdr_qspi;
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u8 ppdsdr_sdram;
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u8 ppdsdr_timerh;
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u8 ppdsdr_timerl;
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u8 ppdsdr_uartl;
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u8 ppdsdr_fec1h;
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u8 ppdsdr_fec1l;
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u8 ppdsdr_bs;
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u8 ppdsdr_res4;
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u8 ppdsdr_usbh;
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u8 ppdsdr_usbl;
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u8 ppdsdr_uarth;
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u8 ppdsdr_res5[3];
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/* Port Clear Output Data Registers */
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u8 pclrr_res1[4];
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u8 pclrr_busctl;
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u8 pclrr_addr;
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u8 pclrr_res2[2];
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u8 pclrr_cs;
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u8 pclrr_res3;
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u8 pclrr_fec0h;
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u8 pclrr_fec0l;
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u8 pclrr_feci2c;
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u8 pclrr_qspi;
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u8 pclrr_sdram;
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u8 pclrr_timerh;
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u8 pclrr_timerl;
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u8 pclrr_uartl;
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u8 pclrr_fec1h;
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u8 pclrr_fec1l;
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u8 pclrr_bs;
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u8 pclrr_res4;
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u8 pclrr_usbh;
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u8 pclrr_usbl;
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u8 pclrr_uarth;
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u8 pclrr_res5[3];
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/* Pin Assignment Registers */
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u8 par_addr;
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u8 par_cs;
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u16 par_busctl;
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u8 par_res1[2];
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u16 par_usb;
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u8 par_fec0hl;
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u8 par_fec1hl;
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u16 par_timer;
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u16 par_uart;
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u16 par_qspi;
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u16 par_sdram;
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u16 par_feci2c;
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u8 par_bs;
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u8 par_res2[3];
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} gpio_t;
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/* Watchdog registers
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*/
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typedef struct wdog_ctrl {
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u16 wcr;
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u16 wmr;
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u16 wcntr;
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u16 wsr;
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u8 res4[114];
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} wdog_t;
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/* USB module registers
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*/
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typedef struct usb {
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u16 res1;
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u16 fnr;
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u16 res2;
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u16 fnmr;
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u16 res3;
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u16 rfmr;
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u16 res4;
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u16 rfmmr;
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u8 res5[3];
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u8 far;
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u32 asr;
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u32 drr1;
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u32 drr2;
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u16 res6;
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u16 specr;
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u16 res7;
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u16 ep0sr;
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u32 iep0cfg;
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u32 oep0cfg;
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u32 ep1cfg;
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u32 ep2cfg;
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u32 ep3cfg;
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u32 ep4cfg;
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u32 ep5cfg;
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u32 ep6cfg;
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u32 ep7cfg;
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u32 ep0ctl;
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u16 res8;
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u16 ep1ctl;
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u16 res9;
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u16 ep2ctl;
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u16 res10;
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u16 ep3ctl;
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u16 res11;
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u16 ep4ctl;
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u16 res12;
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u16 ep5ctl;
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u16 res13;
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u16 ep6ctl;
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u16 res14;
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u16 ep7ctl;
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u32 ep0isr;
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u16 res15;
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u16 ep1isr;
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u16 res16;
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u16 ep2isr;
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u16 res17;
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u16 ep3isr;
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u16 res18;
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u16 ep4isr;
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u16 res19;
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u16 ep5isr;
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u16 res20;
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u16 ep6isr;
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u16 res21;
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u16 ep7isr;
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u32 ep0imr;
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u16 res22;
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u16 ep1imr;
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u16 res23;
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u16 ep2imr;
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u16 res24;
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u16 ep3imr;
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u16 res25;
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u16 ep4imr;
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u16 res26;
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u16 ep5imr;
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u16 res27;
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u16 ep6imr;
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u16 res28;
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u16 ep7imr;
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u32 ep0dr;
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u32 ep1dr;
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u32 ep2dr;
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u32 ep3dr;
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u32 ep4dr;
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u32 ep5dr;
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|
|
|
u32 ep6dr;
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|
|
|
u32 ep7dr;
|
|
|
|
|
u16 res29;
|
|
|
|
|
u16 ep0dpr;
|
|
|
|
|
u16 res30;
|
|
|
|
|
u16 ep1dpr;
|
|
|
|
|
u16 res31;
|
|
|
|
|
u16 ep2dpr;
|
|
|
|
|
u16 res32;
|
|
|
|
|
u16 ep3dpr;
|
|
|
|
|
u16 res33;
|
|
|
|
|
u16 ep4dpr;
|
|
|
|
|
u16 res34;
|
|
|
|
|
u16 ep5dpr;
|
|
|
|
|
u16 res35;
|
|
|
|
|
u16 ep6dpr;
|
|
|
|
|
u16 res36;
|
|
|
|
|
u16 ep7dpr;
|
|
|
|
|
u8 res37[788];
|
|
|
|
|
u8 cfgram[1024];
|
|
|
|
|
} usb_t;
|
|
|
|
|
|
|
|
|
|
/* PLL module registers
|
|
|
|
|
*/
|
|
|
|
|
typedef struct pll_ctrl {
|
|
|
|
|
u32 syncr;
|
|
|
|
|
u32 synsr;
|
|
|
|
|
} pll_t;
|
|
|
|
|
|
|
|
|
|
typedef struct rcm {
|
|
|
|
|
u8 rcr;
|
|
|
|
|
u8 rsr;
|
|
|
|
|
} rcm_t;
|
|
|
|
|
|
|
|
|
|
#endif /* __IMMAP_5275__ */
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