2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-10-14 16:55:50 +00:00
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/**
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* (C) Copyright 2014, Cavium Inc.
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**/
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#ifndef __THUNDERX_88XX_H__
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#define __THUNDERX_88XX_H__
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#define CONFIG_THUNDERX
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#define CONFIG_SYS_64BIT
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#define MEM_BASE 0x00500000
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2015-10-14 16:55:51 +00:00
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#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
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2015-10-14 16:55:50 +00:00
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/* Link Definitions */
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/* SMP Spin Table Definitions */
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#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 24000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE (0x801000000000)
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#define GICR_BASE (0x801000002000)
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#define CONFIG_SYS_SERIAL0 0x87e024000000
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#define CONFIG_SYS_SERIAL1 0x87e025000000
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/* Miscellaneous configurable options */
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Initial environment variables */
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#define UBOOT_IMG_HEAD_SIZE 0x40
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/* C80000 - 0x40 */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=08007ffc0\0" \
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"fdt_addr=0x94C00000\0" \
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"fdt_high=0x9fffffff\0"
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/* Do not preserve environment */
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#define PLL_REF_CLK 50000000 /* 50 MHz */
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#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
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#endif /* __THUNDERX_88XX_H__ */
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