2014-07-30 05:08:14 +00:00
|
|
|
CONFIG_PPC=y
|
2018-02-03 17:10:38 +00:00
|
|
|
CONFIG_SYS_TEXT_BASE=0xFE000000
|
2019-11-19 01:02:10 +00:00
|
|
|
CONFIG_ENV_SIZE=0x4000
|
|
|
|
CONFIG_ENV_SECT_SIZE=0x20000
|
2019-01-21 08:17:53 +00:00
|
|
|
CONFIG_SYS_CLK_FREQ=32000000
|
2014-07-30 05:08:14 +00:00
|
|
|
CONFIG_MPC83xx=y
|
2019-01-21 08:17:56 +00:00
|
|
|
CONFIG_HIGH_BATS=y
|
2014-07-30 05:08:14 +00:00
|
|
|
CONFIG_TARGET_VE8313=y
|
2019-01-21 08:17:54 +00:00
|
|
|
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
|
|
CONFIG_CORE_PLL_RATIO_25_1=y
|
|
|
|
CONFIG_PCI_HOST_MODE_ENABLE=y
|
|
|
|
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
|
|
|
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
|
|
|
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
|
|
CONFIG_LALE_TIMING_EARLIER=y
|
2019-01-21 08:17:57 +00:00
|
|
|
CONFIG_BAT0=y
|
|
|
|
CONFIG_BAT0_NAME="SDRAM"
|
|
|
|
CONFIG_BAT0_BASE=0x00000000
|
|
|
|
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT0_ACCESS_RW=y
|
|
|
|
CONFIG_BAT0_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT1=y
|
|
|
|
CONFIG_BAT1_NAME="PCI_MEM"
|
|
|
|
CONFIG_BAT1_BASE=0x80000000
|
|
|
|
CONFIG_BAT1_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT1_ACCESS_RW=y
|
|
|
|
CONFIG_BAT1_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT2=y
|
|
|
|
CONFIG_BAT2_NAME="PCI_MMIO"
|
|
|
|
CONFIG_BAT2_BASE=0x90000000
|
|
|
|
CONFIG_BAT2_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT2_ACCESS_RW=y
|
|
|
|
CONFIG_BAT2_ICACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT2_ICACHE_GUARDED=y
|
|
|
|
CONFIG_BAT2_DCACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT2_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT2_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT5=y
|
|
|
|
CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR"
|
|
|
|
CONFIG_BAT5_BASE=0xE0000000
|
|
|
|
CONFIG_BAT5_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT5_ACCESS_RW=y
|
|
|
|
CONFIG_BAT5_ICACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT5_ICACHE_GUARDED=y
|
|
|
|
CONFIG_BAT5_DCACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT5_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT5_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT6=y
|
|
|
|
CONFIG_BAT6_NAME="INITRAM_FLASH"
|
|
|
|
CONFIG_BAT6_BASE=0xF0000000
|
|
|
|
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT6_ACCESS_RW=y
|
|
|
|
CONFIG_BAT6_ICACHE_GUARDED=y
|
|
|
|
CONFIG_BAT6_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT6_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT7=y
|
|
|
|
CONFIG_BAT7_NAME="FPGA_SRAM_NAND"
|
|
|
|
CONFIG_BAT7_BASE=0x60000000
|
|
|
|
CONFIG_BAT7_LENGTH_256_MBYTES=y
|
|
|
|
CONFIG_BAT7_ACCESS_RW=y
|
|
|
|
CONFIG_BAT7_ICACHE_GUARDED=y
|
|
|
|
CONFIG_BAT7_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT7_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
|
2019-01-21 08:17:58 +00:00
|
|
|
CONFIG_NAND_LBLAWBAR_PRELIM_1=y
|
|
|
|
CONFIG_LBLAW0=y
|
|
|
|
CONFIG_LBLAW0_BASE=0xFE000000
|
|
|
|
CONFIG_LBLAW0_NAME="FLASH"
|
|
|
|
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
|
|
CONFIG_LBLAW1=y
|
|
|
|
CONFIG_LBLAW1_BASE=0x61000000
|
|
|
|
CONFIG_LBLAW1_NAME="NAND"
|
|
|
|
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_ELBC_BR0_OR0=y
|
|
|
|
CONFIG_BR0_OR0_NAME="FLASH"
|
|
|
|
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
|
|
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
|
|
CONFIG_OR0_AM_32_MBYTES=y
|
|
|
|
CONFIG_OR0_SCY_5=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR0_CSNT_EARLIER=y
|
|
|
|
CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_OR0_TRLX_RELAXED=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR0_EAD_EXTRA=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_ELBC_BR1_OR1=y
|
|
|
|
CONFIG_BR1_OR1_NAME="NAND"
|
|
|
|
CONFIG_BR1_OR1_BASE=0x61000000
|
|
|
|
CONFIG_BR1_ERRORCHECKING_BOTH=y
|
|
|
|
CONFIG_BR1_MACHINE_FCM=y
|
|
|
|
CONFIG_OR1_BCTLD_NOT_ASSERTED=y
|
|
|
|
CONFIG_OR1_SCY_2=y
|
|
|
|
CONFIG_OR1_CHT_TWO_CLOCK=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR1_RST_ONE_CLOCK=y
|
|
|
|
CONFIG_OR1_TRLX_RELAXED=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_ELBC_BR2_OR2=y
|
|
|
|
CONFIG_BR2_OR2_NAME="NVRAM"
|
|
|
|
CONFIG_BR2_OR2_BASE=0x60000000
|
|
|
|
CONFIG_OR2_AM_128_KBYTES=y
|
|
|
|
CONFIG_OR2_SCY_3=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR2_CSNT_EARLIER=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_OR2_XACS_EXTENDED=y
|
|
|
|
CONFIG_OR2_TRLX_RELAXED=y
|
|
|
|
CONFIG_OR2_EHTR_8_CYCLE=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR2_EAD_EXTRA=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_ELBC_BR3_OR3=y
|
|
|
|
CONFIG_BR3_OR3_NAME="SRAM"
|
|
|
|
CONFIG_BR3_OR3_BASE=0x62000000
|
|
|
|
CONFIG_BR3_PORTSIZE_16BIT=y
|
|
|
|
CONFIG_OR3_AM_32_MBYTES=y
|
|
|
|
CONFIG_OR3_SCY_15=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR3_CSNT_EARLIER=y
|
2019-01-21 08:18:03 +00:00
|
|
|
CONFIG_OR3_XACS_EXTENDED=y
|
|
|
|
CONFIG_OR3_TRLX_RELAXED=y
|
|
|
|
CONFIG_OR3_EHTR_8_CYCLE=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OR3_EAD_EXTRA=y
|
|
|
|
CONFIG_HID0_FINAL_EMCP=y
|
|
|
|
CONFIG_HID0_FINAL_ICE=y
|
|
|
|
CONFIG_HID2_HBE=y
|
|
|
|
CONFIG_ACR_PIPE_DEP_4=y
|
|
|
|
CONFIG_ACR_RPTCNT_4=y
|
2019-01-21 08:18:14 +00:00
|
|
|
CONFIG_LCRR_EADC_3=y
|
|
|
|
CONFIG_LCRR_CLKDIV_2=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_OF_BOARD_SETUP=y
|
|
|
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
|
|
CONFIG_BOOTDELAY=6
|
|
|
|
CONFIG_BOARD_EARLY_INIT_F=y
|
|
|
|
CONFIG_HUSH_PARSER=y
|
|
|
|
CONFIG_CMD_IMLS=y
|
|
|
|
CONFIG_CMD_NAND=y
|
|
|
|
CONFIG_CMD_PCI=y
|
|
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
|
|
CONFIG_CMD_DHCP=y
|
|
|
|
CONFIG_CMD_MII=y
|
|
|
|
CONFIG_CMD_PING=y
|
2019-11-10 16:28:03 +00:00
|
|
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
2019-11-19 01:02:10 +00:00
|
|
|
CONFIG_ENV_ADDR=0xFE060000
|
|
|
|
CONFIG_ENV_ADDR_REDUND=0xFE080000
|
2019-05-26 18:45:25 +00:00
|
|
|
# CONFIG_MMC is not set
|
2019-12-04 22:18:38 +00:00
|
|
|
CONFIG_MTD=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_MTD_NOR_FLASH=y
|
|
|
|
CONFIG_FLASH_CFI_DRIVER=y
|
|
|
|
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
|
|
CONFIG_SYS_FLASH_CFI=y
|
2019-12-04 22:18:38 +00:00
|
|
|
CONFIG_MTD_RAW_NAND=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_PHY_MARVELL=y
|
|
|
|
CONFIG_TSEC_ENET=y
|
|
|
|
CONFIG_SYS_NS16550=y
|
|
|
|
CONFIG_OF_LIBFDT=y
|