2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2015-01-28 05:13:31 +00:00
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/*
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* Copyright (c) 2015, Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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* All rights reserved.
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*/
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#include <common.h>
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2016-07-18 10:51:39 +00:00
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#include <dm.h>
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2021-07-05 12:29:02 +00:00
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#include <dm/device_compat.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2015-01-28 05:13:31 +00:00
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#include <pci.h>
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2021-07-05 12:29:02 +00:00
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#include <reset.h>
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2015-01-28 05:13:31 +00:00
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#include <usb.h>
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2019-09-11 09:33:46 +00:00
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#include <usb/xhci.h>
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2015-01-28 05:13:31 +00:00
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2021-07-05 12:29:02 +00:00
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struct xhci_pci_plat {
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struct reset_ctl reset;
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};
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2021-01-18 11:30:04 +00:00
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static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
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struct xhci_hcor **ret_hcor)
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2016-07-18 10:51:39 +00:00
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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u32 cmd;
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hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
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PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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2021-01-18 11:30:04 +00:00
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if (!hccr) {
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printf("xhci-pci init cannot map PCI mem bar\n");
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return -EIO;
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}
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2016-07-18 10:51:39 +00:00
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hcor = (struct xhci_hcor *)((uintptr_t) hccr +
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HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
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2018-06-04 02:04:14 +00:00
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debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n",
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hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
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2016-07-18 10:51:39 +00:00
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*ret_hccr = hccr;
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*ret_hcor = hcor;
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/* enable busmaster */
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dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER;
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dm_pci_write_config32(dev, PCI_COMMAND, cmd);
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2021-01-18 11:30:04 +00:00
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return 0;
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2016-07-18 10:51:39 +00:00
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}
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static int xhci_pci_probe(struct udevice *dev)
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{
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2021-07-05 12:29:02 +00:00
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struct xhci_pci_plat *plat = dev_get_plat(dev);
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2016-07-18 10:51:39 +00:00
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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2021-01-18 11:30:04 +00:00
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int ret;
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2016-07-18 10:51:39 +00:00
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2021-07-05 12:29:02 +00:00
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ret = reset_get_by_index(dev, 0, &plat->reset);
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if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
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dev_err(dev, "failed to get reset\n");
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return ret;
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}
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if (reset_valid(&plat->reset)) {
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ret = reset_assert(&plat->reset);
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if (ret)
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goto err_reset;
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ret = reset_deassert(&plat->reset);
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if (ret)
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goto err_reset;
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}
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2021-01-18 11:30:04 +00:00
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ret = xhci_pci_init(dev, &hccr, &hcor);
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if (ret)
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2021-07-05 12:29:02 +00:00
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goto err_reset;
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ret = xhci_register(dev, hccr, hcor);
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if (ret)
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goto err_reset;
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return 0;
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err_reset:
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if (reset_valid(&plat->reset))
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reset_free(&plat->reset);
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return ret;
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}
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static int xhci_pci_remove(struct udevice *dev)
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{
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struct xhci_pci_plat *plat = dev_get_plat(dev);
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2016-07-18 10:51:39 +00:00
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2021-07-05 12:29:02 +00:00
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xhci_deregister(dev);
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if (reset_valid(&plat->reset))
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reset_free(&plat->reset);
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return 0;
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2016-07-18 10:51:39 +00:00
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}
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static const struct udevice_id xhci_pci_ids[] = {
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{ .compatible = "xhci-pci" },
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{ }
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};
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U_BOOT_DRIVER(xhci_pci) = {
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.name = "xhci_pci",
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.id = UCLASS_USB,
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.probe = xhci_pci_probe,
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2021-07-05 12:29:02 +00:00
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.remove = xhci_pci_remove,
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2016-07-18 10:51:39 +00:00
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.of_match = xhci_pci_ids,
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.ops = &xhci_usb_ops,
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2021-07-05 12:29:02 +00:00
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.plat_auto = sizeof(struct xhci_pci_plat),
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2020-12-03 23:55:17 +00:00
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.priv_auto = sizeof(struct xhci_ctrl),
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2021-01-14 15:49:00 +00:00
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.flags = DM_FLAG_OS_PREPARE | DM_FLAG_ALLOC_PRIV_DMA,
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2016-07-18 10:51:39 +00:00
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};
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static struct pci_device_id xhci_pci_supported[] = {
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{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) },
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{},
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};
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U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported);
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