2019-12-09 00:40:13 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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2021-01-24 17:06:04 +00:00
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#define LOG_CATEGORY LOGC_BOOT
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2019-12-09 00:40:13 +00:00
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#include <common.h>
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#include <binman_sym.h>
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2020-05-10 17:40:00 +00:00
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#include <bootstage.h>
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2019-12-09 00:40:13 +00:00
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#include <dm.h>
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2020-05-10 17:40:01 +00:00
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#include <image.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2019-12-09 00:40:13 +00:00
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#include <spi.h>
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#include <spl.h>
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#include <spi_flash.h>
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#include <asm/fast_spi.h>
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#include <asm/spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/iomap.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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/* This reads the next phase from mapped SPI flash */
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static int rom_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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ulong spl_pos = spl_get_image_pos();
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ulong spl_size = spl_get_image_size();
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struct udevice *dev;
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ulong map_base;
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size_t map_size;
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uint offset;
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int ret;
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spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
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spl_image->entry_point = spl_get_image_text_base();
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2019-12-09 00:40:13 +00:00
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spl_image->load_addr = spl_image->entry_point;
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spl_image->os = IH_OS_U_BOOT;
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spl_image->name = "U-Boot";
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log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size);
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2019-12-09 00:40:13 +00:00
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if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
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ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
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if (ret)
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return log_msg_ret("spi_flash", ret);
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if (!dev)
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return log_msg_ret("spi_flash dev", -ENODEV);
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ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
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if (ret)
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return log_msg_ret("mmap", ret);
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} else {
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ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
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&offset);
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if (ret)
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return ret;
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}
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spl_pos += map_base & ~0xff000000;
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log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos,
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spl_image->load_addr);
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2019-12-09 00:40:13 +00:00
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bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
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memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
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cpu_flush_l1d_to_l2();
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bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
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#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
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static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
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void *buf)
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{
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struct spi_flash *flash = dev_get_uclass_priv(dev);
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struct mtd_info *mtd = &flash->mtd;
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size_t retlen;
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return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
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}
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static int apl_flash_probe(struct udevice *dev)
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{
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return spi_flash_std_probe(dev);
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}
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static const struct dm_spi_flash_ops apl_flash_ops = {
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.read = apl_flash_std_read,
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};
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static const struct udevice_id apl_flash_ids[] = {
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{ .compatible = "jedec,spi-nor" },
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{ }
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};
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U_BOOT_DRIVER(winbond_w25q128fw) = {
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.name = "winbond_w25q128fw",
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.id = UCLASS_SPI_FLASH,
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.of_match = apl_flash_ids,
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.probe = apl_flash_probe,
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.priv_auto = sizeof(struct spi_nor),
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.ops = &apl_flash_ops,
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};
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/* This uses a SPI flash device to read the next phase */
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static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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ulong spl_pos = spl_get_image_pos();
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ulong spl_size = spl_get_image_size();
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
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if (ret)
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return ret;
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spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
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spl_image->entry_point = spl_phase() == PHASE_TPL ?
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CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
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spl_image->load_addr = spl_image->entry_point;
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spl_image->os = IH_OS_U_BOOT;
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spl_image->name = "U-Boot";
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spl_pos &= ~0xff000000;
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log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
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2019-12-09 00:40:13 +00:00
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ret = spi_flash_read_dm(dev, spl_pos, spl_size,
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(void *)spl_image->load_addr);
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cpu_flush_l1d_to_l2();
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if (ret)
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return ret;
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
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spl_fast_spi_load_image);
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void board_boot_order(u32 *spl_boot_list)
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{
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bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
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if (use_spi_flash) {
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spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
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spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
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} else {
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spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
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spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
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}
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}
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#else
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
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}
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#endif
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