2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2017-02-22 08:56:35 +00:00
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/*
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* Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_RK3399_H
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#define _ASM_ARCH_SDRAM_RK3399_H
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struct rk3399_ddr_pctl_regs {
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u32 denali_ctl[332];
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};
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struct rk3399_ddr_publ_regs {
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u32 denali_phy[959];
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};
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struct rk3399_ddr_pi_regs {
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u32 denali_pi[200];
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};
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2019-07-16 11:57:05 +00:00
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union noc_ddrtimingc0 {
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u32 d32;
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struct {
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unsigned burstpenalty : 4;
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unsigned reserved0 : 4;
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unsigned wrtomwr : 6;
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unsigned reserved1 : 18;
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} b;
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};
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2019-07-16 11:57:06 +00:00
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union noc_ddrmode {
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u32 d32;
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struct {
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unsigned autoprecharge : 1;
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unsigned bypassfiltering : 1;
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unsigned fawbank : 1;
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unsigned burstsize : 2;
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unsigned mwrsize : 2;
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unsigned reserved2 : 1;
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unsigned forceorder : 8;
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unsigned forceorderstate : 8;
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unsigned reserved3 : 8;
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} b;
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};
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2017-02-22 08:56:35 +00:00
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struct rk3399_msch_regs {
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u32 coreid;
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u32 revisionid;
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u32 ddrconf;
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u32 ddrsize;
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u32 ddrtiminga0;
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u32 ddrtimingb0;
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u32 ddrtimingc0;
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u32 devtodev0;
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u32 reserved0[(0x110 - 0x20) / 4];
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u32 ddrmode;
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u32 reserved1[(0x1000 - 0x114) / 4];
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u32 agingx0;
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};
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struct rk3399_msch_timings {
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u32 ddrtiminga0;
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u32 ddrtimingb0;
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2019-07-16 11:57:05 +00:00
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union noc_ddrtimingc0 ddrtimingc0;
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2017-02-22 08:56:35 +00:00
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u32 devtodev0;
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2019-07-16 11:57:06 +00:00
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union noc_ddrmode ddrmode;
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2017-02-22 08:56:35 +00:00
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u32 agingx0;
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};
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struct rk3399_ddr_cic_regs {
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u32 cic_ctrl0;
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u32 cic_ctrl1;
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u32 cic_idle_th;
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u32 cic_cg_wait_th;
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u32 cic_status0;
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u32 cic_status1;
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u32 cic_ctrl2;
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u32 cic_ctrl3;
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u32 cic_ctrl4;
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};
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/* DENALI_CTL_00 */
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#define START 1
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/* DENALI_CTL_68 */
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#define PWRUP_SREFRESH_EXIT (1 << 16)
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/* DENALI_CTL_274 */
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#define MEM_RST_VALID 1
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2019-07-15 18:21:05 +00:00
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struct rk3399_sdram_channel {
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struct sdram_cap_info cap_info;
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2017-02-22 08:56:35 +00:00
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struct rk3399_msch_timings noc_timings;
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};
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struct rk3399_sdram_params {
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struct rk3399_sdram_channel ch[2];
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2019-07-15 18:21:06 +00:00
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struct sdram_base_params base;
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2017-02-22 08:56:35 +00:00
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struct rk3399_ddr_pctl_regs pctl_regs;
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struct rk3399_ddr_pi_regs pi_regs;
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struct rk3399_ddr_publ_regs phy_regs;
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};
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#define PI_CA_TRAINING (1 << 0)
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#define PI_WRITE_LEVELING (1 << 1)
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#define PI_READ_GATE_TRAINING (1 << 2)
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#define PI_READ_LEVELING (1 << 3)
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#define PI_WDQ_LEVELING (1 << 4)
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#define PI_FULL_TRAINING 0xff
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#endif
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