2020-06-23 11:15:08 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Siemens AG, 2020
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* Derived from linux/drivers/watchdog/rti_wdt.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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2021-09-18 06:17:55 +00:00
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#include <dm/device_compat.h>
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2020-06-23 11:15:08 +00:00
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#include <power-domain.h>
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#include <wdt.h>
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#include <asm/io.h>
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2021-09-18 06:17:55 +00:00
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#include <remoteproc.h>
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2020-06-23 11:15:08 +00:00
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/* Timer register set definition */
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#define RTIDWDCTRL 0x90
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#define RTIDWDPRLD 0x94
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#define RTIWDSTATUS 0x98
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#define RTIWDKEY 0x9c
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#define RTIDWDCNTR 0xa0
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#define RTIWWDRXCTRL 0xa4
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#define RTIWWDSIZECTRL 0xa8
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#define RTIWWDRX_NMI 0xa
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#define RTIWWDSIZE_50P 0x50
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#define WDENABLE_KEY 0xa98559da
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#define WDKEY_SEQ0 0xe51a
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#define WDKEY_SEQ1 0xa35c
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#define WDT_PRELOAD_SHIFT 13
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#define WDT_PRELOAD_MAX 0xfff
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struct rti_wdt_priv {
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phys_addr_t regs;
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2022-03-08 06:25:50 +00:00
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unsigned int clk_hz;
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2020-06-23 11:15:08 +00:00
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};
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2021-09-18 06:17:55 +00:00
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#ifdef CONFIG_WDT_K3_RTI_LOAD_FW
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#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware"
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static int rti_wdt_load_fw(struct udevice *dev)
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{
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struct udevice *rproc_dev;
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int primary_core, ret;
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u32 cluster_mode;
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ofnode node;
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u64 rti_wdt_fw;
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u32 rti_wdt_fw_size;
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node = ofnode_path(RTI_WDT_FIT_PATH);
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if (!ofnode_valid(node))
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goto fit_error;
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ret = ofnode_read_u64(node, "load", &rti_wdt_fw);
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if (ret)
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goto fit_error;
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ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size);
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if (ret)
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goto fit_error;
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node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss");
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if (!ofnode_valid(node))
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goto dt_error;
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ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode);
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if (ret)
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cluster_mode = 1;
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node = ofnode_by_compatible(node, "ti,am654-r5f");
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if (!ofnode_valid(node))
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goto dt_error;
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ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev);
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if (ret)
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return ret;
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primary_core = dev_seq(rproc_dev);
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ret = rproc_dev_init(primary_core);
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if (ret)
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goto fw_error;
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if (cluster_mode == 1) {
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ret = rproc_dev_init(primary_core + 1);
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if (ret)
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goto fw_error;
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}
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ret = rproc_load(primary_core, (ulong)rti_wdt_fw,
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rti_wdt_fw_size);
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if (ret)
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goto fw_error;
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ret = rproc_start(primary_core);
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if (ret)
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goto fw_error;
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return 0;
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fit_error:
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dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH);
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return -ENOENT;
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dt_error:
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dev_err(dev, "No compatible firmware target processor found\n");
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return -ENODEV;
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fw_error:
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dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n",
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primary_core);
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return ret;
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}
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#else
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static inline int rti_wdt_load_fw(struct udevice *dev)
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{
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return 0;
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}
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#endif
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2020-06-23 11:15:08 +00:00
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static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct rti_wdt_priv *priv = dev_get_priv(dev);
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u32 timer_margin;
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int ret;
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if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY)
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return -EBUSY;
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2021-09-18 06:17:55 +00:00
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ret = rti_wdt_load_fw(dev);
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if (ret < 0)
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return ret;
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2022-03-08 06:25:50 +00:00
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timer_margin = timeout_ms * priv->clk_hz / 1000;
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2020-06-23 11:15:08 +00:00
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timer_margin >>= WDT_PRELOAD_SHIFT;
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if (timer_margin > WDT_PRELOAD_MAX)
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timer_margin = WDT_PRELOAD_MAX;
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writel(timer_margin, priv->regs + RTIDWDPRLD);
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writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL);
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writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL);
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readl(priv->regs + RTIWWDSIZECTRL);
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writel(WDENABLE_KEY, priv->regs + RTIDWDCTRL);
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return 0;
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}
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static int rti_wdt_reset(struct udevice *dev)
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{
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struct rti_wdt_priv *priv = dev_get_priv(dev);
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u32 prld;
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/* Make sure we do not reset too early */
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prld = readl(priv->regs + RTIDWDPRLD) << WDT_PRELOAD_SHIFT;
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if (readl(priv->regs + RTIDWDCNTR) >= prld / 2)
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return -EPERM;
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writel(WDKEY_SEQ0, priv->regs + RTIWDKEY);
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writel(WDKEY_SEQ1, priv->regs + RTIWDKEY);
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return 0;
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}
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static int rti_wdt_probe(struct udevice *dev)
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{
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struct rti_wdt_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret;
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priv->regs = devfdt_get_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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2022-03-08 06:25:50 +00:00
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priv->clk_hz = clk_get_rate(&clk);
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/*
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* If watchdog is running at 32k clock, it is not accurate.
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* Adjust frequency down in this case so that it does not expire
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* earlier than expected.
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*/
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if (priv->clk_hz < 32768)
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priv->clk_hz = priv->clk_hz * 9 / 10;
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2020-06-23 11:15:08 +00:00
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return 0;
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}
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static const struct wdt_ops rti_wdt_ops = {
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.start = rti_wdt_start,
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.reset = rti_wdt_reset,
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};
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static const struct udevice_id rti_wdt_ids[] = {
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{ .compatible = "ti,j7-rti-wdt" },
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{ }
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};
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U_BOOT_DRIVER(rti_wdt) = {
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.name = "rti_wdt",
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.id = UCLASS_WDT,
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.of_match = rti_wdt_ids,
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.ops = &rti_wdt_ops,
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.probe = rti_wdt_probe,
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2020-12-03 23:55:17 +00:00
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.priv_auto = sizeof(struct rti_wdt_priv),
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2021-01-24 21:32:42 +00:00
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.flags = DM_FLAG_LEAVE_PD_ON,
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2020-06-23 11:15:08 +00:00
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};
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