u-boot/drivers/clk/ti/Kconfig

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
#

config CLK_TI_AM3_DPLL
	bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
	depends on CLK && OF_CONTROL
	help
	  This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
	  provides all interface clocks and functional clocks to the processor.

config CLK_TI_DIVIDER
	bool "TI divider clock driver"
	depends on CLK && OF_CONTROL && CLK_CCF
	help
	  This enables the divider clock driver support on TI's SoCs.

config CLK_TI_GATE
	bool "TI gate clock driver"
	depends on CLK && OF_CONTROL
	help
	  This enables the gate clock driver support on TI's SoCs.

config CLK_TI_MUX
	bool "TI mux clock driver"
	depends on CLK && OF_CONTROL && CLK_CCF
	help
	  This enables the mux clock driver support on TI's SoCs.
clk: ti: add mux clock driver The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it> 2020-12-29 23:06:32 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>`
			`#`

clk: ti: am33xx: add DPLL clock drivers The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it> 2020-12-29 23:06:34 +00:00			`config CLK_TI_AM3_DPLL`
			`bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"`
			`depends on CLK && OF_CONTROL`
			`help`
			`This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL`
			`provides all interface clocks and functional clocks to the processor.`

clk: ti: add divider clock driver The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by: Dario Binacchi <dariobin@libero.it> 2020-12-29 23:06:35 +00:00			`config CLK_TI_DIVIDER`
			`bool "TI divider clock driver"`
			`depends on CLK && OF_CONTROL && CLK_CCF`
			`help`
			`This enables the divider clock driver support on TI's SoCs.`

clk: ti: add gate clock driver The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi <dariobin@libero.it> 2020-12-29 23:06:36 +00:00			`config CLK_TI_GATE`
			`bool "TI gate clock driver"`
			`depends on CLK && OF_CONTROL`
			`help`
			`This enables the gate clock driver support on TI's SoCs.`

clk: ti: add mux clock driver The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it> 2020-12-29 23:06:32 +00:00			`config CLK_TI_MUX`
			`bool "TI mux clock driver"`
			`depends on CLK && OF_CONTROL && CLK_CCF`
			`help`
			`This enables the mux clock driver support on TI's SoCs.`