mirror of
https://github.com/AsahiLinux/u-boot
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548 lines
13 KiB
Text
548 lines
13 KiB
Text
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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* Copyright 2019-2020 Variscite Ltd.
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* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#include "imx8mn.dtsi"
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/ {
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model = "Variscite VAR-SOM-MX8MN module";
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compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
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chosen {
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stdout-path = &uart4;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x40000000>;
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};
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reg_eth_phy: regulator-eth-phy {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_eth_phy>;
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regulator-name = "eth_phy_pwr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_1 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_2 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_3 {
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cpu-supply = <&buck2_reg>;
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
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<&gpio1 0 GPIO_ACTIVE_LOW>;
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/delete-property/ dmas;
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/delete-property/ dma-names;
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status = "okay";
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/* Resistive touch controller */
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touchscreen@0 {
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reg = <0>;
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compatible = "ti,ads7846";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_restouch>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
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spi-max-frequency = <1500000>;
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pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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ti,x-min = /bits/ 16 <125>;
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touchscreen-size-x = /bits/ 16 <4008>;
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ti,y-min = /bits/ 16 <282>;
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touchscreen-size-y = /bits/ 16 <3864>;
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ti,x-plate-ohms = /bits/ 16 <180>;
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touchscreen-max-pressure = /bits/ 16 <255>;
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touchscreen-average-samples = /bits/ 16 <10>;
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ti,debounce-tol = /bits/ 16 <3>;
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ti,debounce-rep = /bits/ 16 <1>;
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ti,settle-delay-usec = /bits/ 16 <150>;
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ti,keep-vref-on;
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wakeup-source;
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};
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};
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&fec1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_fec1>;
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pinctrl-1 = <&pinctrl_fec1_sleep>;
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phy-mode = "rgmii";
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phy-handle = <ðphy>;
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phy-supply = <®_eth_phy>;
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phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio2>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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buck2_reg: BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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buck3_reg: BUCK3 {
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4_reg: BUCK4 {
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regulator-name = "buck4";
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regulator-min-microvolt = <2600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5_reg: BUCK5 {
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regulator-name = "buck5";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: BUCK6 {
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regulator-name = "buck6";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <1900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: LDO4 {
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regulator-name = "ldo4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo5_reg: LDO5 {
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regulator-compatible = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo6_reg: LDO6 {
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regulator-name = "ldo6";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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/* TODO: configure audio, as of now just put a placeholder */
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wm8904: codec@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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status = "disabled";
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* Bluetooth */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MN_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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/* Console */
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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/* WIFI */
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&usdhc1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <4>;
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non-removable;
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keep-power-in-suspend;
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status = "okay";
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brcmf: bcrmf@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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/* SD */
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&usdhc2 {
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assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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/* eMMC */
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&usdhc3 {
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assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
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MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
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MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
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MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
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MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_fec1_sleep: fec1sleepgrp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
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MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
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MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
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|
|
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
|
||
|
|
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||
|
|
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||
|
|
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pmic: pmicirqgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_eth_phy: regethphygrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_restouch: restouchgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
|
||
|
|
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
|
||
|
|
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
|
||
|
|
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart4: uart4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
|
||
|
|
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|