Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-06 13:14:27 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/mach-uniphier/clk/pll-pro4.c

110 lines
3 KiB
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*/
ARM: uniphier: replace <common.h> with <linux/delay.h> where possible The <common.h> includes too many headers. Actually, these files needed to include it for udelay() declaration. Now we can replace it with <linux/delay.h> thanks to commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-21 09:05:25 +00:00
#include <linux/delay.h>
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#include "pll.h"
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
/* Set VPLL27A & VPLL27B */
ARM: uniphier: de-couple SG macros into base address and offset The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:40 +00:00
tmp = readl(sg_base + SG_PINMON0);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
return;
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x00000001;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL);
tmp = readl(sc_base + SC_VPLL27BCTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x00000001;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
/* Unset VPLA_K_LD and VPLB_K_LD bit */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL3);
tmp = readl(sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
/* Set VPLA_M and VPLB_M to 0x20 */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x0000007f;
tmp |= 0x00000020;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL2);
tmp = readl(sc_base + SC_VPLL27BCTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x0000007f;
tmp |= 0x00000020;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
/* Set VPLA_K and VPLB_K for AXO: 25MHz */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x000fffff;
tmp |= 0x00066666;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL3);
tmp = readl(sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x000fffff;
tmp |= 0x00066666;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
} else {
/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL3);
tmp = readl(sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
}
/* wait 1 usec */
udelay(1);
/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL3);
tmp = readl(sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL3);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
/* Unset VPLA_SNRST and VPLB_SNRST bit */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL2);
tmp = readl(sc_base + SC_VPLL27BCTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp |= 0x10000000;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL2);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
tmp = readl(sc_base + SC_VPLL27ACTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x00000001;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27ACTRL);
tmp = readl(sc_base + SC_VPLL27BCTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
tmp &= ~0x00000001;
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
writel(tmp, sc_base + SC_VPLL27BCTRL);
ARM: uniphier: move PLL init code to U-Boot proper where possible The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:09 +00:00
}
void uniphier_pro4_pll_init(void)
{
vpll_init();
uniphier_ld4_dpll_ssc_en();
}
Reference in a new issue Copy permalink