2018-05-06 22:27:01 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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2017-04-28 05:11:35 +00:00
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/*
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* NXP ls2080a RDB board device tree source for QSPI-boot
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*
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* Author: Priyanka Jain <priyanka.jain@nxp.com>
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*
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* Copyright 2017 NXP
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*/
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/dts-v1/;
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#include "fsl-ls2080a.dtsi"
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/ {
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model = "Freescale Layerscape 2080a RDB Board";
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compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
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aliases {
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spi0 = &qspi;
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spi1 = &dspi;
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};
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};
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&dspi {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q512a {
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#address-cells = <1>;
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#size-cells = <1>;
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2019-02-10 10:16:20 +00:00
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compatible = "jedec,spi-nor";
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2017-04-28 05:11:35 +00:00
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fs512s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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2019-02-10 10:16:20 +00:00
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compatible = "jedec,spi-nor";
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2017-04-28 05:11:35 +00:00
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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qflash1: s25fs512s@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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2019-02-10 10:16:20 +00:00
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compatible = "jedec,spi-nor";
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2017-04-28 05:11:35 +00:00
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spi-max-frequency = <50000000>;
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reg = <1>;
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};
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};
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2018-12-27 04:37:59 +00:00
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2019-07-22 08:36:46 +00:00
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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pca9547@75 {
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compatible = "nxp,pca9547";
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reg = <0x75>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x01>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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};
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};
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};
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};
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2018-12-27 04:37:59 +00:00
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&sata {
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status = "okay";
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};
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