arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* J721E: SoC specific initialization
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*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/armv7_mpu.h>
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2019-06-13 04:59:43 +00:00
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#include <asm/arch/hardware.h>
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2023-04-06 16:38:16 +00:00
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#include "sysfw-loader.h"
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arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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#include "common.h"
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2019-06-13 04:59:46 +00:00
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#include <linux/soc/ti/ti_sci_protocol.h>
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2019-06-13 04:59:47 +00:00
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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2022-02-09 09:36:53 +00:00
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#include <dm/root.h>
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#include <fdtdec.h>
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2020-02-26 08:14:36 +00:00
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#include <mmc.h>
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2020-02-12 08:25:04 +00:00
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#include <remoteproc.h>
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arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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2020-01-10 19:35:21 +00:00
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#ifdef CONFIG_K3_LOAD_SYSFW
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struct fwl_data cbass_hc_cfg0_fwls[] = {
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{ "PCIE0_CFG", 2560, 8 },
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{ "PCIE1_CFG", 2561, 8 },
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{ "USB3SS0_CORE", 2568, 4 },
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{ "USB3SS1_CORE", 2570, 4 },
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{ "EMMC8SS0_CFG", 2576, 4 },
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{ "UFS_HCI0_CFG", 2580, 4 },
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{ "SERDES0", 2584, 1 },
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{ "SERDES1", 2585, 1 },
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}, cbass_hc0_fwls[] = {
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{ "PCIE0_HP", 2528, 24 },
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{ "PCIE0_LP", 2529, 24 },
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{ "PCIE1_HP", 2530, 24 },
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{ "PCIE1_LP", 2531, 24 },
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}, cbass_rc_cfg0_fwls[] = {
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{ "EMMCSD4SS0_CFG", 2380, 4 },
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}, cbass_rc0_fwls[] = {
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{ "GPMC0", 2310, 8 },
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}, infra_cbass0_fwls[] = {
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{ "PLL_MMR0", 8, 26 },
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{ "CTRL_MMR0", 9, 16 },
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}, mcu_cbass0_fwls[] = {
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{ "MCU_R5FSS0_CORE0", 1024, 4 },
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{ "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
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{ "MCU_R5FSS0_CORE1", 1028, 4 },
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{ "MCU_FSS0_CFG", 1032, 12 },
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{ "MCU_FSS0_S1", 1033, 8 },
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{ "MCU_FSS0_S0", 1036, 8 },
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{ "MCU_PSROM49152X32", 1048, 1 },
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{ "MCU_MSRAM128KX64", 1050, 8 },
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{ "MCU_CTRL_MMR0", 1200, 8 },
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{ "MCU_PLL_MMR0", 1201, 3 },
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{ "MCU_CPSW0", 1220, 2 },
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}, wkup_cbass0_fwls[] = {
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{ "WKUP_CTRL_MMR0", 131, 16 },
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};
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#endif
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2019-06-13 04:59:44 +00:00
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 3);
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mmr_unlock(CTRL_MMR0_BASE, 5);
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2020-08-05 17:14:20 +00:00
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if (soc_is_j721e())
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mmr_unlock(CTRL_MMR0_BASE, 6);
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2019-06-13 04:59:44 +00:00
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mmr_unlock(CTRL_MMR0_BASE, 7);
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}
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2020-02-26 08:14:36 +00:00
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#if defined(CONFIG_K3_LOAD_SYSFW)
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void k3_mmc_stop_clock(void)
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{
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if (spl_boot_device() == BOOT_DEVICE_MMC1) {
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struct mmc *mmc = find_mmc_device(0);
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if (!mmc)
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return;
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mmc->saved_clock = mmc->clock;
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mmc_set_clock(mmc, 0, true);
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}
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}
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void k3_mmc_restart_clock(void)
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{
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if (spl_boot_device() == BOOT_DEVICE_MMC1) {
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struct mmc *mmc = find_mmc_device(0);
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if (!mmc)
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return;
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mmc_set_clock(mmc, mmc->saved_clock, false);
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}
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}
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#endif
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2019-06-13 04:59:45 +00:00
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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2021-05-20 11:23:52 +00:00
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u32 bootindex __section(".data");
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static struct rom_extended_boot_data bootdata __section(".data");
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2019-06-13 04:59:45 +00:00
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2020-08-05 17:14:22 +00:00
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static void store_boot_info_from_rom(void)
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2019-06-13 04:59:45 +00:00
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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2022-11-22 19:28:11 +00:00
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memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
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2020-08-05 17:14:22 +00:00
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sizeof(struct rom_extended_boot_data));
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2019-06-13 04:59:45 +00:00
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}
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2022-02-09 09:36:53 +00:00
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#ifdef CONFIG_SPL_OF_LIST
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void do_dt_magic(void)
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{
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int ret, rescan, mmc_dev = -1;
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static struct mmc *mmc;
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2023-04-06 16:38:17 +00:00
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/* Perform board detection */
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do_board_detect();
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2022-02-09 09:36:53 +00:00
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/*
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* Board detection has been done.
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* Let us see if another dtb wouldn't be a better match
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* for our board
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*/
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if (IS_ENABLED(CONFIG_CPU_V7R)) {
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ret = fdtdec_resetup(&rescan);
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if (!ret && rescan) {
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dm_uninit();
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dm_init_and_scan(true);
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}
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}
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/*
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* Because of multi DTB configuration, the MMC device has
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* to be re-initialized after reconfiguring FDT inorder to
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* boot from MMC. Do this when boot mode is MMC and ROM has
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* not loaded SYSFW.
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*/
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC1:
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mmc_dev = 0;
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break;
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case BOOT_DEVICE_MMC2:
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case BOOT_DEVICE_MMC2_2:
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mmc_dev = 1;
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break;
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}
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if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
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ret = mmc_init_device(mmc_dev);
|
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|
|
if (!ret) {
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|
mmc = find_mmc_device(mmc_dev);
|
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|
if (mmc) {
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ret = mmc_init(mmc);
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|
|
if (ret) {
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|
printf("mmc init failed with error: %d\n", ret);
|
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|
}
|
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}
|
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|
}
|
|
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|
}
|
|
|
|
}
|
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|
|
#endif
|
|
|
|
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
void board_init_f(ulong dummy)
|
|
|
|
{
|
2019-10-07 13:56:38 +00:00
|
|
|
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
|
2019-06-13 04:59:47 +00:00
|
|
|
struct udevice *dev;
|
|
|
|
int ret;
|
|
|
|
#endif
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
/*
|
2019-06-13 04:59:45 +00:00
|
|
|
* Cannot delay this further as there is a chance that
|
|
|
|
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
*/
|
2020-08-05 17:14:22 +00:00
|
|
|
store_boot_info_from_rom();
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
|
2019-06-13 04:59:44 +00:00
|
|
|
/* Make all control module registers accessible */
|
|
|
|
ctrl_mmr_unlock();
|
|
|
|
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
#ifdef CONFIG_CPU_V7R
|
2019-12-31 10:19:55 +00:00
|
|
|
disable_linefill_optimization();
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
setup_k3_mpu_regions();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Init DM early */
|
|
|
|
spl_early_init();
|
|
|
|
|
2019-06-13 04:59:47 +00:00
|
|
|
#ifdef CONFIG_K3_LOAD_SYSFW
|
|
|
|
/*
|
|
|
|
* Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
|
|
|
|
* regardless of the result of pinctrl. Do this without probing the
|
|
|
|
* device, but instead by searching the device that would request the
|
|
|
|
* given sequence number if probed. The UART will be used by the system
|
|
|
|
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
|
|
|
* to initialize its pin settings.
|
|
|
|
*/
|
2020-12-17 04:20:29 +00:00
|
|
|
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
2019-06-13 04:59:47 +00:00
|
|
|
if (!ret)
|
|
|
|
pinctrl_select_state(dev, "default");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Load, start up, and configure system controller firmware. Provide
|
|
|
|
* the U-Boot console init function to the SYSFW post-PM configuration
|
|
|
|
* callback hook, effectively switching on (or over) the console
|
|
|
|
* output.
|
|
|
|
*/
|
2020-08-05 17:14:23 +00:00
|
|
|
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
|
|
|
|
k3_mmc_stop_clock, k3_mmc_restart_clock);
|
2020-02-26 08:14:36 +00:00
|
|
|
|
2022-02-09 09:36:53 +00:00
|
|
|
#ifdef CONFIG_SPL_OF_LIST
|
|
|
|
do_dt_magic();
|
|
|
|
#endif
|
|
|
|
|
2021-06-11 08:45:23 +00:00
|
|
|
/*
|
|
|
|
* Force probe of clk_k3 driver here to ensure basic default clock
|
|
|
|
* configuration is always done.
|
|
|
|
*/
|
|
|
|
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
|
|
|
DM_DRIVER_GET(ti_clk),
|
|
|
|
&dev);
|
|
|
|
if (ret)
|
|
|
|
panic("Failed to initialize clk-k3!\n");
|
|
|
|
}
|
|
|
|
|
2020-02-26 08:14:36 +00:00
|
|
|
/* Prepare console output */
|
|
|
|
preloader_console_init();
|
2020-01-10 19:35:21 +00:00
|
|
|
|
|
|
|
/* Disable ROM configured firewalls right after loading sysfw */
|
|
|
|
remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
|
|
|
|
remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
|
|
|
|
remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
|
|
|
|
remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
|
|
|
|
remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
|
|
|
|
remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
|
|
|
|
remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
|
2019-06-13 04:59:47 +00:00
|
|
|
#else
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
/* Prepare console output */
|
|
|
|
preloader_console_init();
|
2019-06-13 04:59:47 +00:00
|
|
|
#endif
|
2019-10-07 13:56:38 +00:00
|
|
|
|
2020-03-10 11:20:58 +00:00
|
|
|
/* Output System Firmware version info */
|
|
|
|
k3_sysfw_print_ver();
|
|
|
|
|
2023-04-06 16:38:17 +00:00
|
|
|
/* Perform board detection */
|
|
|
|
do_board_detect();
|
2020-01-07 07:45:54 +00:00
|
|
|
|
2019-10-24 09:30:53 +00:00
|
|
|
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
2020-12-29 03:34:56 +00:00
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
|
2019-10-24 09:30:53 +00:00
|
|
|
&dev);
|
|
|
|
if (ret)
|
|
|
|
printf("AVS init failed: %d\n", ret);
|
|
|
|
#endif
|
|
|
|
|
2019-10-07 13:56:38 +00:00
|
|
|
#if defined(CONFIG_K3_J721E_DDRSS)
|
|
|
|
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
|
|
|
if (ret)
|
|
|
|
panic("DRAM init failed: %d\n", ret);
|
|
|
|
#endif
|
2020-05-18 05:57:22 +00:00
|
|
|
spl_enable_dcache();
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
}
|
2019-06-13 04:59:43 +00:00
|
|
|
|
2021-07-12 10:06:49 +00:00
|
|
|
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
2019-06-13 04:59:43 +00:00
|
|
|
{
|
|
|
|
switch (boot_device) {
|
|
|
|
case BOOT_DEVICE_MMC1:
|
|
|
|
return MMCSD_MODE_EMMCBOOT;
|
|
|
|
case BOOT_DEVICE_MMC2:
|
|
|
|
return MMCSD_MODE_FS;
|
|
|
|
default:
|
|
|
|
return MMCSD_MODE_RAW;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-16 15:35:01 +00:00
|
|
|
static u32 __get_backup_bootmedia(u32 main_devstat)
|
|
|
|
{
|
|
|
|
u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
|
|
|
|
MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
|
|
|
|
|
|
|
|
switch (bkup_boot) {
|
|
|
|
case BACKUP_BOOT_DEVICE_USB:
|
|
|
|
return BOOT_DEVICE_DFU;
|
|
|
|
case BACKUP_BOOT_DEVICE_UART:
|
|
|
|
return BOOT_DEVICE_UART;
|
|
|
|
case BACKUP_BOOT_DEVICE_ETHERNET:
|
|
|
|
return BOOT_DEVICE_ETHERNET;
|
|
|
|
case BACKUP_BOOT_DEVICE_MMC2:
|
|
|
|
{
|
|
|
|
u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
|
|
|
|
MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
|
|
|
|
if (port == 0x0)
|
|
|
|
return BOOT_DEVICE_MMC1;
|
|
|
|
return BOOT_DEVICE_MMC2;
|
|
|
|
}
|
|
|
|
case BACKUP_BOOT_DEVICE_SPI:
|
|
|
|
return BOOT_DEVICE_SPI;
|
|
|
|
case BACKUP_BOOT_DEVICE_I2C:
|
|
|
|
return BOOT_DEVICE_I2C;
|
|
|
|
}
|
|
|
|
|
|
|
|
return BOOT_DEVICE_RAM;
|
|
|
|
}
|
|
|
|
|
2019-06-13 04:59:43 +00:00
|
|
|
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
|
|
|
|
{
|
|
|
|
|
|
|
|
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
|
|
|
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
|
|
|
|
|
|
|
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
|
|
|
|
BOOT_MODE_B_SHIFT;
|
|
|
|
|
|
|
|
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
|
|
|
|
bootmode = BOOT_DEVICE_SPI;
|
|
|
|
|
|
|
|
if (bootmode == BOOT_DEVICE_MMC2) {
|
|
|
|
u32 port = (main_devstat &
|
|
|
|
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
|
|
|
|
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
|
|
|
|
if (port == 0x0)
|
|
|
|
bootmode = BOOT_DEVICE_MMC1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return bootmode;
|
|
|
|
}
|
|
|
|
|
2022-06-03 06:02:16 +00:00
|
|
|
u32 spl_spi_boot_bus(void)
|
|
|
|
{
|
|
|
|
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
|
|
|
|
u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
|
|
|
u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
|
|
|
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
|
|
|
|
((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT);
|
|
|
|
|
|
|
|
return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
2019-06-13 04:59:43 +00:00
|
|
|
u32 spl_boot_device(void)
|
|
|
|
{
|
|
|
|
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
|
|
|
|
u32 main_devstat;
|
|
|
|
|
|
|
|
if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
|
|
|
|
printf("ERROR: MCU only boot is not yet supported\n");
|
|
|
|
return BOOT_DEVICE_RAM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
|
|
|
|
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
|
|
|
|
2020-05-16 15:35:01 +00:00
|
|
|
if (bootindex == K3_PRIMARY_BOOTMODE)
|
|
|
|
return __get_primary_bootmedia(main_devstat, wkup_devstat);
|
|
|
|
else
|
|
|
|
return __get_backup_bootmedia(main_devstat);
|
2019-06-13 04:59:43 +00:00
|
|
|
}
|