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u-boot/board/tbs/tbs2910/tbs2910.cfg

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
board: tbs2910: add private imx config Add board specific imx config file with recommended IPU Qos settings and adapted DDR configuration. Signed-off-by: Soeren Moch <smoch@web.de>
2018-01-28 11:26:34 +00:00
/*
* Copyright (C) 2017 Soeren Moch <smoch@web.de>
*/
#define __ASSEMBLY__
#include "asm/arch/crm_regs.h"
#include "asm/arch/iomux.h"
#include "asm/arch/mx6-ddr.h"
/* image version 2 for imx6 */
IMAGE_VERSION 2
BOOT_FROM sd
/* set the default clock gates to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
DATA 4, CCM_CCOSR, 0x000000fb
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x77177717
DATA 4, MX6_IOMUXC_GPR7, 0x77177717
/*
* DDR3/DDR3L settings
* use default 40 Ohm pad drive strength, no odt
* 4x256Mx16 DDR3L-1066 7-7-7
*/
/* disable dq pullup */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
/* disable dqs pullup */
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
/* set ddr input mode for dq signals */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
/* set ddr input mode for dqs signals */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
/* set pad calibration type to DDR3 */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* ZQ calibration */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
/* dqs write delay */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
/* dqs read delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* dqs read gating control */
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
/* start delay line calibration */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
/* ODT timing */
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
/* read odt settings, 120 Ohm */
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
/* 2GiByte RAM at cs0 */
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
/* load mode registers of external ddr chips */
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
/* externel chip ZQ calibration */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
/* configure and start refreshes, 8 refresh commands at 32 kHz */
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
/* set automatic self refresh */
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
/* controller configuration finished */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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