2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2014-10-22 10:13:17 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2009
|
|
|
|
* Marvell Semiconductor <www.marvell.com>
|
|
|
|
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
|
|
|
*/
|
|
|
|
|
2015-04-25 04:29:47 +00:00
|
|
|
#ifndef _MVEBU_CPU_H
|
|
|
|
#define _MVEBU_CPU_H
|
2014-10-22 10:13:17 +00:00
|
|
|
|
|
|
|
#include <asm/system.h>
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
|
|
|
|
#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
|
|
|
|
|
|
|
|
enum memory_bank {
|
|
|
|
BANK0,
|
|
|
|
BANK1,
|
|
|
|
BANK2,
|
|
|
|
BANK3
|
|
|
|
};
|
|
|
|
|
|
|
|
enum cpu_winen {
|
|
|
|
CPU_WIN_DISABLE,
|
|
|
|
CPU_WIN_ENABLE
|
|
|
|
};
|
|
|
|
|
|
|
|
enum cpu_target {
|
|
|
|
CPU_TARGET_DRAM = 0x0,
|
|
|
|
CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
|
|
|
|
CPU_TARGET_ETH23 = 0x3,
|
|
|
|
CPU_TARGET_PCIE02 = 0x4,
|
|
|
|
CPU_TARGET_ETH01 = 0x7,
|
|
|
|
CPU_TARGET_PCIE13 = 0x8,
|
2019-04-11 10:22:50 +00:00
|
|
|
CPU_TARGET_DFX = 0x8,
|
2014-10-22 10:13:17 +00:00
|
|
|
CPU_TARGET_SASRAM = 0x9,
|
2017-01-11 15:01:00 +00:00
|
|
|
CPU_TARGET_SATA01 = 0xa, /* A38X */
|
2014-10-22 10:13:17 +00:00
|
|
|
CPU_TARGET_NAND = 0xd,
|
2017-01-11 15:01:00 +00:00
|
|
|
CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
|
2014-10-22 10:13:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
enum cpu_attrib {
|
|
|
|
CPU_ATTR_SASRAM = 0x01,
|
|
|
|
CPU_ATTR_DRAM_CS0 = 0x0e,
|
|
|
|
CPU_ATTR_DRAM_CS1 = 0x0d,
|
|
|
|
CPU_ATTR_DRAM_CS2 = 0x0b,
|
|
|
|
CPU_ATTR_DRAM_CS3 = 0x07,
|
|
|
|
CPU_ATTR_NANDFLASH = 0x2f,
|
|
|
|
CPU_ATTR_SPIFLASH = 0x1e,
|
2016-02-12 12:52:16 +00:00
|
|
|
CPU_ATTR_SPI0_CS0 = 0x1e,
|
|
|
|
CPU_ATTR_SPI0_CS1 = 0x5e,
|
|
|
|
CPU_ATTR_SPI1_CS2 = 0x9a,
|
2014-10-22 10:13:17 +00:00
|
|
|
CPU_ATTR_BOOTROM = 0x1d,
|
|
|
|
CPU_ATTR_PCIE_IO = 0xe0,
|
|
|
|
CPU_ATTR_PCIE_MEM = 0xe8,
|
|
|
|
CPU_ATTR_DEV_CS0 = 0x3e,
|
|
|
|
CPU_ATTR_DEV_CS1 = 0x3d,
|
|
|
|
CPU_ATTR_DEV_CS2 = 0x3b,
|
|
|
|
CPU_ATTR_DEV_CS3 = 0x37,
|
|
|
|
};
|
|
|
|
|
2015-04-25 04:29:51 +00:00
|
|
|
enum {
|
|
|
|
MVEBU_SOC_AXP,
|
2016-02-10 06:23:00 +00:00
|
|
|
MVEBU_SOC_A375,
|
2015-04-25 04:29:51 +00:00
|
|
|
MVEBU_SOC_A38X,
|
2017-09-04 05:38:31 +00:00
|
|
|
MVEBU_SOC_MSYS,
|
2015-04-25 04:29:51 +00:00
|
|
|
MVEBU_SOC_UNKNOWN,
|
|
|
|
};
|
|
|
|
|
2018-10-22 12:21:17 +00:00
|
|
|
#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
|
|
|
|
|
2014-10-22 10:13:17 +00:00
|
|
|
/*
|
|
|
|
* Default Device Address MAP BAR values
|
|
|
|
*/
|
2018-10-22 12:21:17 +00:00
|
|
|
#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
|
2015-07-01 10:55:07 +00:00
|
|
|
#define MBUS_PCI_MEM_SIZE (128 << 20)
|
|
|
|
#define MBUS_PCI_IO_BASE 0xF1100000
|
|
|
|
#define MBUS_PCI_IO_SIZE (64 << 10)
|
|
|
|
#define MBUS_SPI_BASE 0xF4000000
|
|
|
|
#define MBUS_SPI_SIZE (8 << 20)
|
2019-04-11 10:22:50 +00:00
|
|
|
#define MBUS_DFX_BASE 0xF6000000
|
|
|
|
#define MBUS_DFX_SIZE (1 << 20)
|
2015-07-01 10:55:07 +00:00
|
|
|
#define MBUS_BOOTROM_BASE 0xF8000000
|
|
|
|
#define MBUS_BOOTROM_SIZE (8 << 20)
|
2014-10-22 10:13:17 +00:00
|
|
|
|
|
|
|
struct mbus_win {
|
|
|
|
u32 base;
|
|
|
|
u32 size;
|
|
|
|
u8 target;
|
|
|
|
u8 attr;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* System registers
|
|
|
|
* Ref: Datasheet sec:A.28
|
|
|
|
*/
|
|
|
|
struct mvebu_system_registers {
|
2016-02-10 06:23:00 +00:00
|
|
|
#if defined(CONFIG_ARMADA_375)
|
|
|
|
u8 pad1[0x54];
|
|
|
|
#else
|
2014-10-22 10:13:17 +00:00
|
|
|
u8 pad1[0x60];
|
2016-02-10 06:23:00 +00:00
|
|
|
#endif
|
2014-10-22 10:13:17 +00:00
|
|
|
u32 rstoutn_mask; /* 0x60 */
|
|
|
|
u32 sys_soft_rst; /* 0x64 */
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GPIO Registers
|
|
|
|
* Ref: Datasheet sec:A.19
|
|
|
|
*/
|
|
|
|
struct kwgpio_registers {
|
|
|
|
u32 dout;
|
|
|
|
u32 oe;
|
|
|
|
u32 blink_en;
|
|
|
|
u32 din_pol;
|
|
|
|
u32 din;
|
|
|
|
u32 irq_cause;
|
|
|
|
u32 irq_mask;
|
|
|
|
u32 irq_level;
|
|
|
|
};
|
|
|
|
|
2015-12-21 11:36:40 +00:00
|
|
|
struct sar_freq_modes {
|
|
|
|
u8 val;
|
|
|
|
u8 ffc; /* Fabric Frequency Configuration */
|
|
|
|
u32 p_clk;
|
|
|
|
u32 nb_clk;
|
|
|
|
u32 d_clk;
|
|
|
|
};
|
|
|
|
|
2015-01-19 10:33:47 +00:00
|
|
|
/* Needed for dynamic (board-specific) mbus configuration */
|
|
|
|
extern struct mvebu_mbus_state mbus_state;
|
|
|
|
|
2014-10-22 10:13:17 +00:00
|
|
|
/*
|
|
|
|
* functions
|
|
|
|
*/
|
|
|
|
unsigned int mvebu_sdram_bar(enum memory_bank bank);
|
|
|
|
unsigned int mvebu_sdram_bs(enum memory_bank bank);
|
|
|
|
void mvebu_sdram_size_adjust(enum memory_bank bank);
|
|
|
|
int mvebu_mbus_probe(struct mbus_win windows[], int count);
|
2015-04-25 04:29:51 +00:00
|
|
|
int mvebu_soc_family(void);
|
2015-07-16 08:40:05 +00:00
|
|
|
u32 mvebu_get_nand_clock(void);
|
2015-01-19 10:33:42 +00:00
|
|
|
|
2021-07-23 09:14:24 +00:00
|
|
|
void __noreturn return_to_bootrom(void);
|
2015-08-25 11:49:41 +00:00
|
|
|
|
2019-04-11 02:56:58 +00:00
|
|
|
#ifndef CONFIG_DM_MMC
|
2015-06-29 12:58:10 +00:00
|
|
|
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
|
2019-04-11 02:56:58 +00:00
|
|
|
#endif
|
2015-06-29 12:58:10 +00:00
|
|
|
|
2015-12-21 11:36:40 +00:00
|
|
|
void get_sar_freq(struct sar_freq_modes *sar_freq);
|
|
|
|
|
2015-01-19 10:33:42 +00:00
|
|
|
/*
|
|
|
|
* Highspeed SERDES PHY config init, ported from bin_hdr
|
|
|
|
* to mainline U-Boot
|
|
|
|
*/
|
|
|
|
int serdes_phy_config(void);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DDR3 init / training code ported from Marvell bin_hdr. Now
|
|
|
|
* available in mainline U-Boot in:
|
2015-03-25 11:51:18 +00:00
|
|
|
* drivers/ddr/marvell
|
2015-01-19 10:33:42 +00:00
|
|
|
*/
|
|
|
|
int ddr3_init(void);
|
2016-01-20 07:13:28 +00:00
|
|
|
|
2019-07-10 15:23:04 +00:00
|
|
|
/* Auto Voltage Scaling */
|
2021-03-05 14:52:42 +00:00
|
|
|
#if defined(CONFIG_ARMADA_38X)
|
2019-07-10 15:23:04 +00:00
|
|
|
void mv_avs_init(void);
|
2020-02-26 06:53:50 +00:00
|
|
|
void mv_rtc_config(void);
|
2019-07-10 15:23:04 +00:00
|
|
|
#else
|
|
|
|
static inline void mv_avs_init(void) {}
|
2020-02-26 06:53:50 +00:00
|
|
|
static inline void mv_rtc_config(void) {}
|
2019-07-10 15:23:04 +00:00
|
|
|
#endif
|
|
|
|
|
2020-04-08 17:25:18 +00:00
|
|
|
/* A8K dram functions */
|
|
|
|
u64 a8k_dram_scan_ap_sz(void);
|
|
|
|
int a8k_dram_init_banksize(void);
|
|
|
|
|
2020-04-08 17:25:19 +00:00
|
|
|
/* A3700 dram functions */
|
|
|
|
int a3700_dram_init(void);
|
|
|
|
int a3700_dram_init_banksize(void);
|
|
|
|
|
2020-04-08 17:25:21 +00:00
|
|
|
/* A3700 PCIe regions fixer for device tree */
|
|
|
|
int a3700_fdt_fix_pcie_regions(void *blob);
|
|
|
|
|
2016-05-17 13:00:30 +00:00
|
|
|
/*
|
|
|
|
* get_ref_clk
|
|
|
|
*
|
|
|
|
* return: reference clock in MHz (25 or 40)
|
|
|
|
*/
|
|
|
|
u32 get_ref_clk(void);
|
|
|
|
|
2014-10-22 10:13:17 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
2015-04-25 04:29:47 +00:00
|
|
|
#endif /* _MVEBU_CPU_H */
|