mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 16:07:30 +00:00
282 lines
7.5 KiB
C
282 lines
7.5 KiB
C
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/********************************************************/
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/* */
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/* Samsung S3C44B0 */
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/* tpu <tapu@371.net> */
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/* */
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/********************************************************/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#define REGBASE 0x01c00000
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#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))
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#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))
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#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))
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/*****************************/
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/* CPU Wrapper Registers */
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/*****************************/
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#define SYSCFG REGL(0x000000)
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#define NCACHBE0 REGL(0x000004)
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#define NCACHBE1 REGL(0x000008)
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#define SBUSCON REGL(0x040000)
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/************************************/
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/* Memory Controller Registers */
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/************************************/
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#define BWSCON REGL(0x080000)
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#define BANKCON0 REGL(0x080004)
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#define BANKCON1 REGL(0x080008)
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#define BANKCON2 REGL(0x08000c)
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#define BANKCON3 REGL(0x080010)
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#define BANKCON4 REGL(0x080014)
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#define BANKCON5 REGL(0x080018)
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#define BANKCON6 REGL(0x08001c)
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#define BANKCON7 REGL(0x080020)
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#define REFRESH REGL(0x080024)
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#define BANKSIZE REGL(0x080028)
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#define MRSRB6 REGL(0x08002c)
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#define MRSRB7 REGL(0x080030)
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/*********************/
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/* UART Registers */
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/*********************/
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#define ULCON0 REGL(0x100000)
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#define ULCON1 REGL(0x104000)
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#define UCON0 REGL(0x100004)
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#define UCON1 REGL(0x104004)
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#define UFCON0 REGL(0x100008)
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#define UFCON1 REGL(0x104008)
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#define UMCON0 REGL(0x10000c)
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#define UMCON1 REGL(0x10400c)
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#define UTRSTAT0 REGL(0x100010)
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#define UTRSTAT1 REGL(0x104010)
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#define UERSTAT0 REGL(0x100014)
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#define UERSTAT1 REGL(0x104014)
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#define UFSTAT0 REGL(0x100018)
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#define UFSTAT1 REGL(0x104018)
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#define UMSTAT0 REGL(0x10001c)
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#define UMSTAT1 REGL(0x10401c)
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#define UTXH0 REGB(0x100020)
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#define UTXH1 REGB(0x104020)
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#define URXH0 REGB(0x100024)
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#define URXH1 REGB(0x104024)
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#define UBRDIV0 REGL(0x100028)
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#define UBRDIV1 REGL(0x104028)
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/*******************/
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/* SIO Registers */
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/*******************/
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#define SIOCON REGL(0x114000)
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#define SIODAT REGL(0x114004)
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#define SBRDR REGL(0x114008)
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#define ITVCNT REGL(0x11400c)
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#define DCNTZ REGL(0x114010)
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/********************/
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/* IIS Registers */
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/********************/
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#define IISCON REGL(0x118000)
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#define IISMOD REGL(0x118004)
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#define IISPSR REGL(0x118008)
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#define IISFIFCON REGL(0x11800c)
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#define IISFIF REGW(0x118010)
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/**************************/
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/* I/O Ports Registers */
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/**************************/
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#define PCONA REGL(0x120000)
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#define PDATA REGL(0x120004)
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#define PCONB REGL(0x120008)
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#define PDATB REGL(0x12000c)
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#define PCONC REGL(0x120010)
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#define PDATC REGL(0x120014)
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#define PUPC REGL(0x120018)
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#define PCOND REGL(0x12001c)
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#define PDATD REGL(0x120020)
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#define PUPD REGL(0x120024)
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#define PCONE REGL(0x120028)
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#define PDATE REGL(0x12002c)
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#define PUPE REGL(0x120030)
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#define PCONF REGL(0x120034)
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#define PDATF REGL(0x120038)
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#define PUPF REGL(0x12003c)
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#define PCONG REGL(0x120040)
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#define PDATG REGL(0x120044)
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#define PUPG REGL(0x120048)
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#define SPUCR REGL(0x12004c)
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#define EXTINT REGL(0x120050)
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#define EXTINTPND REGL(0x120054)
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/*********************************/
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/* WatchDog Timers Registers */
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/*********************************/
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#define WTCON REGL(0x130000)
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#define WTDAT REGL(0x130004)
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#define WTCNT REGL(0x130008)
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/*********************************/
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/* A/D Converter Registers */
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/*********************************/
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#define ADCCON REGL(0x140000)
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#define ADCPSR REGL(0x140004)
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#define ADCDAT REGL(0x140008)
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/***************************/
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/* PWM Timer Registers */
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/***************************/
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#define TCFG0 REGL(0x150000)
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#define TCFG1 REGL(0x150004)
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#define TCON REGL(0x150008)
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#define TCNTB0 REGL(0x15000c)
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#define TCMPB0 REGL(0x150010)
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#define TCNTO0 REGL(0x150014)
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#define TCNTB1 REGL(0x150018)
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#define TCMPB1 REGL(0x15001c)
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#define TCNTO1 REGL(0x150020)
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#define TCNTB2 REGL(0x150024)
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#define TCMPB2 REGL(0x150028)
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#define TCNTO2 REGL(0x15002c)
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#define TCNTB3 REGL(0x150030)
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#define TCMPB3 REGL(0x150034)
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#define TCNTO3 REGL(0x150038)
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#define TCNTB4 REGL(0x15003c)
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#define TCMPB4 REGL(0x150040)
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#define TCNTO4 REGL(0x150044)
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#define TCNTB5 REGL(0x150048)
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#define TCNTO5 REGL(0x15004c)
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/*********************/
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/* IIC Registers */
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/*********************/
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#define IICCON REGL(0x160000)
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#define IICSTAT REGL(0x160004)
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#define IICADD REGL(0x160008)
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#define IICDS REGL(0x16000c)
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/*********************/
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/* RTC Registers */
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/*********************/
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#define RTCCON REGB(0x170040)
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#define RTCALM REGB(0x170050)
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#define ALMSEC REGB(0x170054)
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#define ALMMIN REGB(0x170058)
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#define ALMHOUR REGB(0x17005c)
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#define ALMDAY REGB(0x170060)
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#define ALMMON REGB(0x170064)
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#define ALMYEAR REGB(0x170068)
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#define RTCRST REGB(0x17006c)
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#define BCDSEC REGB(0x170070)
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#define BCDMIN REGB(0x170074)
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#define BCDHOUR REGB(0x170078)
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#define BCDDAY REGB(0x17007c)
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#define BCDDATE REGB(0x170080)
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#define BCDMON REGB(0x170084)
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#define BCDYEAR REGB(0x170088)
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#define TICINT REGB(0x17008c)
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/*********************************/
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/* Clock & Power Registers */
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/*********************************/
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#define PLLCON REGL(0x180000)
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#define CLKCON REGL(0x180004)
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#define CLKSLOW REGL(0x180008)
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#define LOCKTIME REGL(0x18000c)
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/**************************************/
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/* Interrupt Controller Registers */
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/**************************************/
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#define INTCON REGL(0x200000)
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#define INTPND REGL(0x200004)
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#define INTMOD REGL(0x200008)
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#define INTMSK REGL(0x20000c)
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#define I_PSLV REGL(0x200010)
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#define I_PMST REGL(0x200014)
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#define I_CSLV REGL(0x200018)
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#define I_CMST REGL(0x20001c)
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#define I_ISPR REGL(0x200020)
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#define I_ISPC REGL(0x200024)
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#define F_ISPR REGL(0x200038)
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#define F_ISPC REGL(0x20003c)
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/********************************/
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/* LCD Controller Registers */
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/********************************/
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#define LCDCON1 REGL(0x300000)
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#define LCDCON2 REGL(0x300004)
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#define LCDSADDR1 REGL(0x300008)
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#define LCDSADDR2 REGL(0x30000c)
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#define LCDSADDR3 REGL(0x300010)
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#define REDLUT REGL(0x300014)
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#define GREENLUT REGL(0x300018)
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#define BLUELUT REGL(0x30001c)
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#define DP1_2 REGL(0x300020)
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#define DP4_7 REGL(0x300024)
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#define DP3_5 REGL(0x300028)
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#define DP2_3 REGL(0x30002c)
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#define DP5_7 REGL(0x300030)
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#define DP3_4 REGL(0x300034)
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#define DP4_5 REGL(0x300038)
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#define DP6_7 REGL(0x30003c)
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#define LCDCON3 REGL(0x300040)
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#define DITHMODE REGL(0x300044)
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/*********************/
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/* DMA Registers */
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/*********************/
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#define ZDCON0 REGL(0x280000)
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#define ZDISRC0 REGL(0x280004)
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#define ZDIDES0 REGL(0x280008)
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#define ZDICNT0 REGL(0x28000c)
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#define ZDCSRC0 REGL(0x280010)
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#define ZDCDES0 REGL(0x280014)
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#define ZDCCNT0 REGL(0x280018)
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#define ZDCON1 REGL(0x280020)
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#define ZDISRC1 REGL(0x280024)
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#define ZDIDES1 REGL(0x280028)
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#define ZDICNT1 REGL(0x28002c)
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#define ZDCSRC1 REGL(0x280030)
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#define ZDCDES1 REGL(0x280034)
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#define ZDCCNT1 REGL(0x280038)
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#define BDCON0 REGL(0x380000)
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#define BDISRC0 REGL(0x380004)
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#define BDIDES0 REGL(0x380008)
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#define BDICNT0 REGL(0x38000c)
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#define BDCSRC0 REGL(0x380010)
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#define BDCDES0 REGL(0x380014)
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#define BDCCNT0 REGL(0x380018)
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#define BDCON1 REGL(0x380020)
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#define BDISRC1 REGL(0x380024)
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#define BDIDES1 REGL(0x380028)
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#define BDICNT1 REGL(0x38002c)
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#define BDCSRC1 REGL(0x380030)
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#define BDCDES1 REGL(0x380034)
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#define BDCCNT1 REGL(0x380038)
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#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n))
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#define INT_ENABLE(n) INTMSK &= ~(1<<(n))
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#define INT_DISABLE(n) INTMSK |= (1<<(n))
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#define HARD_RESET_NOW()
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#endif /* __ASM_ARCH_HARDWARE_H */
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