2015-09-01 22:41:52 +00:00
|
|
|
CONFIG_ARM=y
|
|
|
|
|
CONFIG_ARCH_SOCFPGA=y
|
2015-09-28 12:14:15 +00:00
|
|
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|
|
|
|
CONFIG_SPL_DM=y
|
|
|
|
|
CONFIG_DM_GPIO=y
|
2015-09-01 22:41:52 +00:00
|
|
|
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
|
|
|
|
|
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
|
|
|
|
|
CONFIG_SPL=y
|
2015-09-28 12:14:15 +00:00
|
|
|
CONFIG_SPL_STACK_R=y
|
|
|
|
|
CONFIG_SPL_STACK_R_ADDR=0x00800000
|
2015-09-01 22:41:52 +00:00
|
|
|
# CONFIG_CMD_IMLS is not set
|
|
|
|
|
# CONFIG_CMD_FLASH is not set
|
2015-09-28 12:14:15 +00:00
|
|
|
CONFIG_SPL_SIMPLE_BUS=y
|
|
|
|
|
CONFIG_DWAPB_GPIO=y
|
2015-09-01 22:41:52 +00:00
|
|
|
CONFIG_DM_ETH=y
|
|
|
|
|
CONFIG_ETH_DESIGNWARE=y
|
