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445 lines
14 KiB
C
445 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#ifndef _S5PXX18_SOC_DPC_H_
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#define _S5PXX18_SOC_DPC_H_
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#include "s5pxx18_soc_disptype.h"
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#define IRQ_OFFSET 32
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#define IRQ_DPC_P (IRQ_OFFSET + 33)
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#define IRQ_DPC_S (IRQ_OFFSET + 34)
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#define NUMBER_OF_DPC_MODULE 2
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#define PHY_BASEADDR_DPC0 0xC0102800
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#define PHY_BASEADDR_DPC1 0xC0102C00
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#define PHY_BASEADDR_DPC_LIST \
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{ PHY_BASEADDR_DPC0, PHY_BASEADDR_DPC1 }
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struct nx_dpc_register_set {
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u32 ntsc_stata;
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u32 ntsc_ecmda;
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u32 ntsc_ecmdb;
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u32 ntsc_glk;
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u32 ntsc_sch;
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u32 ntsc_hue;
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u32 ntsc_sat;
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u32 ntsc_cont;
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u32 ntsc_bright;
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u32 ntsc_fsc_adjh;
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u32 ntsc_fsc_adjl;
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u32 ntsc_ecmdc;
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u32 ntsc_csdly;
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u32 __ntsc_reserved_0_[3];
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u32 ntsc_dacsel10;
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u32 ntsc_dacsel32;
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u32 ntsc_dacsel54;
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u32 ntsc_daclp;
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u32 ntsc_dacpd;
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u32 __ntsc_reserved_1_[(0x20 - 0x15)];
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u32 ntsc_icntl;
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u32 ntsc_hvoffst;
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u32 ntsc_hoffst;
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u32 ntsc_voffset;
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u32 ntsc_hsvso;
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u32 ntsc_hsob;
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u32 ntsc_hsoe;
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u32 ntsc_vsob;
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u32 ntsc_vsoe;
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u32 __reserved[(0xf8 / 4) - 0x29];
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u32 dpchtotal;
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u32 dpchswidth;
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u32 dpchastart;
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u32 dpchaend;
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u32 dpcvtotal;
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u32 dpcvswidth;
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u32 dpcvastart;
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u32 dpcvaend;
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u32 dpcctrl0;
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u32 dpcctrl1;
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u32 dpcevtotal;
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u32 dpcevswidth;
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u32 dpcevastart;
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u32 dpcevaend;
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u32 dpcctrl2;
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u32 dpcvseoffset;
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u32 dpcvssoffset;
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u32 dpcevseoffset;
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u32 dpcevssoffset;
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u32 dpcdelay0;
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u32 dpcupscalecon0;
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u32 dpcupscalecon1;
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u32 dpcupscalecon2;
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u32 dpcrnumgencon0;
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u32 dpcrnumgencon1;
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u32 dpcrnumgencon2;
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u32 dpcrndconformula_l;
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u32 dpcrndconformula_h;
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u32 dpcfdtaddr;
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u32 dpcfrdithervalue;
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u32 dpcfgdithervalue;
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u32 dpcfbdithervalue;
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u32 dpcdelay1;
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u32 dpcmputime0;
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u32 dpcmputime1;
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u32 dpcmpuwrdatal;
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u32 dpcmpuindex;
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u32 dpcmpustatus;
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u32 dpcmpudatah;
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u32 dpcmpurdatal;
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u32 dpcdummy12;
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u32 dpccmdbufferdatal;
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u32 dpccmdbufferdatah;
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u32 dpcpolctrl;
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u32 dpcpadposition[8];
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u32 dpcrgbmask[2];
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u32 dpcrgbshift;
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u32 dpcdataflush;
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u32 __reserved06[((0x3c0) - (2 * 0x0ec)) / 4];
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u32 dpcclkenb;
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u32 dpcclkgen[2][2];
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};
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enum {
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nx_dpc_int_vsync = 0
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};
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enum nx_dpc_format {
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nx_dpc_format_rgb555 = 0ul,
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nx_dpc_format_rgb565 = 1ul,
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nx_dpc_format_rgb666 = 2ul,
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nx_dpc_format_rgb666b = 18ul,
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nx_dpc_format_rgb888 = 3ul,
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nx_dpc_format_mrgb555a = 4ul,
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nx_dpc_format_mrgb555b = 5ul,
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nx_dpc_format_mrgb565 = 6ul,
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nx_dpc_format_mrgb666 = 7ul,
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nx_dpc_format_mrgb888a = 8ul,
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nx_dpc_format_mrgb888b = 9ul,
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nx_dpc_format_ccir656 = 10ul,
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nx_dpc_format_ccir601a = 12ul,
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nx_dpc_format_ccir601b = 13ul,
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nx_dpc_format_srgb888 = 14ul,
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nx_dpc_format_srgbd8888 = 15ul,
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nx_dpc_format_4096color = 1ul,
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nx_dpc_format_16gray = 3ul
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};
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enum nx_dpc_ycorder {
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nx_dpc_ycorder_cb_ycr_y = 0ul,
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nx_dpc_ycorder_cr_ycb_y = 1ul,
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nx_dpc_ycorder_ycbycr = 2ul,
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nx_dpc_ycorder_ycrycb = 3ul
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};
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enum nx_dpc_padclk {
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nx_dpc_padclk_vclk = 0ul,
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nx_dpc_padclk_vclk2 = 1ul,
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nx_dpc_padclk_vclk3 = 2ul
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};
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enum nx_dpc_dither {
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nx_dpc_dither_bypass = 0ul,
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nx_dpc_dither_4bit = 1ul,
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nx_dpc_dither_5bit = 2ul,
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nx_dpc_dither_6bit = 3ul
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};
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enum nx_dpc_vbs {
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nx_dpc_vbs_ntsc_m = 0ul,
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nx_dpc_vbs_ntsc_n = 1ul,
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nx_dpc_vbs_ntsc_443 = 2ul,
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nx_dpc_vbs_pal_m = 3ul,
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nx_dpc_vbs_pal_n = 4ul,
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nx_dpc_vbs_pal_bghi = 5ul,
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nx_dpc_vbs_pseudo_pal = 6ul,
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nx_dpc_vbs_pseudo_ntsc = 7ul
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};
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enum nx_dpc_bandwidth {
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nx_dpc_bandwidth_low = 0ul,
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nx_dpc_bandwidth_medium = 1ul,
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nx_dpc_bandwidth_high = 2ul
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};
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int nx_dpc_initialize(void);
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u32 nx_dpc_get_number_of_module(void);
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u32 nx_dpc_get_physical_address(u32 module_index);
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u32 nx_dpc_get_size_of_register_set(void);
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void nx_dpc_set_base_address(u32 module_index, void *base_address);
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void *nx_dpc_get_base_address(u32 module_index);
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int nx_dpc_open_module(u32 module_index);
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int nx_dpc_close_module(u32 module_index);
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int nx_dpc_check_busy(u32 module_index);
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int nx_dpc_can_power_down(u32 module_index);
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int32_t nx_dpc_get_interrupt_number(u32 module_index);
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void nx_dpc_set_interrupt_enable(u32 module_index, int32_t int_num,
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int enable);
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int nx_dpc_get_interrupt_enable(u32 module_index, int32_t int_num);
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int nx_dpc_get_interrupt_pending(u32 module_index, int32_t int_num);
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void nx_dpc_clear_interrupt_pending(u32 module_index, int32_t int_num);
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void nx_dpc_set_interrupt_enable_all(u32 module_index, int enable);
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int nx_dpc_get_interrupt_enable_all(u32 module_index);
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int nx_dpc_get_interrupt_pending_all(u32 module_index);
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void nx_dpc_clear_interrupt_pending_all(u32 module_index);
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void nx_dpc_set_interrupt_enable32(u32 module_index, u32 enable_flag);
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u32 nx_dpc_get_interrupt_enable32(u32 module_index);
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u32 nx_dpc_get_interrupt_pending32(u32 module_index);
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void nx_dpc_clear_interrupt_pending32(u32 module_index,
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u32 pending_flag);
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int32_t nx_dpc_get_interrupt_pending_number(u32 module_index);
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void nx_dpc_set_clock_pclk_mode(u32 module_index, enum nx_pclkmode mode);
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enum nx_pclkmode nx_dpc_get_clock_pclk_mode(u32 module_index);
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void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src);
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u32 nx_dpc_get_clock_source(u32 module_index, u32 index);
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void nx_dpc_set_clock_divisor(u32 module_index, u32 index, u32 divisor);
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u32 nx_dpc_get_clock_divisor(u32 module_index, u32 index);
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void nx_dpc_set_clock_out_inv(u32 module_index, u32 index,
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int out_clk_inv);
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int nx_dpc_get_clock_out_inv(u32 module_index, u32 index);
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void nx_dpc_set_clock_out_select(u32 module_index, u32 index,
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int bbypass);
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int nx_dpc_get_clock_out_select(u32 module_index, u32 index);
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void nx_dpc_set_clock_polarity(u32 module_index, int bpolarity);
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int nx_dpc_get_clock_polarity(u32 module_index);
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void nx_dpc_set_clock_out_enb(u32 module_index, u32 index,
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int out_clk_enb);
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int nx_dpc_get_clock_out_enb(u32 module_index, u32 index);
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void nx_dpc_set_clock_out_delay(u32 module_index, u32 index, u32 delay);
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u32 nx_dpc_get_clock_out_delay(u32 module_index, u32 index);
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void nx_dpc_set_clock_divisor_enable(u32 module_index, int enable);
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int nx_dpc_get_clock_divisor_enable(u32 module_index);
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void nx_dpc_set_dpc_enable(u32 module_index, int benb);
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int nx_dpc_get_dpc_enable(u32 module_index);
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void nx_dpc_set_delay(u32 module_index, u32 delay_rgb_pvd,
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u32 delay_hs_cp1, u32 delay_vs_fram,
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u32 delay_de_cp2);
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void nx_dpc_get_delay(u32 module_index, u32 *pdelayrgb_pvd,
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u32 *pdelayhs_cp1, u32 *pdelayvs_fram,
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u32 *pdelayde_cp2);
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void nx_dpc_set_dither(u32 module_index, enum nx_dpc_dither dither_r,
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enum nx_dpc_dither dither_g,
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enum nx_dpc_dither dither_b);
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void nx_dpc_get_dither(u32 module_index, enum nx_dpc_dither *pditherr,
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enum nx_dpc_dither *pditherg,
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enum nx_dpc_dither *pditherb);
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void nx_dpc_set_horizontal_up_scaler(u32 module_index, int benb,
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u32 sourcewidth, u32 destwidth);
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void nx_dpc_get_horizontal_up_scaler(u32 module_index, int *pbenb,
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u32 *psourcewidth,
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u32 *pdestwidth);
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void nx_dpc_set_mode(u32 module_index, enum nx_dpc_format format,
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int binterlace, int binvertfield, int brgbmode,
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int bswaprb, enum nx_dpc_ycorder ycorder,
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int bclipyc, int bembeddedsync,
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enum nx_dpc_padclk clock, int binvertclock,
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int bdualview);
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void nx_dpc_get_mode(u32 module_index, enum nx_dpc_format *pformat,
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int *pbinterlace, int *pbinvertfield,
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int *pbrgbmode, int *pbswaprb,
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enum nx_dpc_ycorder *pycorder, int *pbclipyc,
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int *pbembeddedsync, enum nx_dpc_padclk *pclock,
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int *pbinvertclock, int *pbdualview);
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void nx_dpc_set_hsync(u32 module_index, u32 avwidth, u32 hsw, u32 hfp,
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u32 hbp, int binvhsync);
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void nx_dpc_get_hsync(u32 module_index, u32 *pavwidth, u32 *phsw,
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u32 *phfp, u32 *phbp, int *pbinvhsync);
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void nx_dpc_set_vsync(u32 module_index, u32 avheight, u32 vsw, u32 vfp,
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u32 vbp, int binvvsync, u32 eavheight, u32 evsw,
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u32 evfp, u32 evbp);
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void nx_dpc_get_vsync(u32 module_index, u32 *pavheight, u32 *pvsw,
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u32 *pvfp, u32 *pvbp, int *pbinvvsync,
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u32 *peavheight, u32 *pevsw, u32 *pevfp,
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u32 *pevbp);
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void nx_dpc_set_vsync_offset(u32 module_index, u32 vssoffset,
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u32 vseoffset, u32 evssoffset,
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u32 evseoffset);
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void nx_dpc_get_vsync_offset(u32 module_index, u32 *pvssoffset,
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u32 *pvseoffset, u32 *pevssoffset,
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u32 *pevseoffset);
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u32 nx_dpc_enable_pad_tft(u32 module_index, u32 mode_index);
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u32 nx_dpc_enable_pad_i80(u32 module_index, u32 mode_index);
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enum syncgenmode {
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progressive = 0,
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interlace = 1
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};
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enum polarity {
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polarity_activehigh = 0,
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polarity_activelow = 1
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};
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enum outputformat {
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outputformat_rgb555 = 0,
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outputformat_rgb565 = 1,
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outputformat_rgb666 = 2,
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outputformat_rgb888 = 3,
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outputformat_mrgb555a = 4,
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outputformat_mrgb555b = 5,
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outputformat_mrgb565 = 6,
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outputformat_mrgb666 = 7,
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outputformat_mrgb888a = 8,
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outputformat_mrgb888b = 9,
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outputformat_bgr555 = 10,
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outputformat_bgr565 = 11,
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outputformat_bgr666 = 12,
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outputformat_bgr888 = 13,
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outputformat_mbgr555a = 14,
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outputformat_mbgr555b = 15,
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outputformat_mbgr565 = 16,
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outputformat_mbgr666 = 17,
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outputformat_mbgr888a = 18,
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outputformat_mbgr888b = 19,
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outputformat_ccir656 = 20,
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outputformat_ccir601_8 = 21,
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outputformat_ccir601_16a = 22,
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outputformat_ccir601_16b = 23,
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outputformat_srgb888 = 24,
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outputformat_srgbd8888 = 25
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};
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enum outpadclksel {
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padvclk = 0,
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padvclk2 = 1,
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padvclk3 = 2
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};
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enum qmode {
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qmode_220 = 0,
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qmode_256 = 1
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};
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void nx_dpc_set_sync(u32 module_index, enum syncgenmode sync_gen_mode,
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u32 avwidth, u32 avheight, u32 hsw, u32 hfp,
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u32 hbp, u32 vsw, u32 vfp, u32 vbp,
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enum polarity field_polarity,
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enum polarity hsyncpolarity,
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enum polarity vsyncpolarity, u32 even_vsw,
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u32 even_vfp, u32 even_vbp, u32 vsetpixel,
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u32 vsclrpixel, u32 evenvsetpixel,
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u32 evenvsclrpixel);
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void nx_dpc_set_output_format(u32 module_index,
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enum outputformat output_format,
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u8 output_video_config);
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void nx_dpc_set_quantization_mode(u32 module_index, enum qmode rgb2yc,
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enum qmode yc2rgb);
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void nx_dpc_set_enable(u32 module_index, int enable, int rgbmode,
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int use_ntscsync, int use_analog_output,
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int seavenable);
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void nx_dpc_set_enable_with_interlace(u32 module_index, int enable,
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int rgbmode, int use_ntscsync,
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int use_analog_output,
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int seavenable);
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void nx_dpc_set_enable_with_interlace(u32 module_index, int enable,
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int rgbmode, int use_ntscsync,
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int use_analog_output,
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int seavenable);
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void nx_dpc_set_out_video_clk_select(u32 module_index,
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enum outpadclksel out_pad_vclk_sel);
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void nx_dpc_set_reg_flush(u32 module_index);
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void nx_dpc_set_sramon(u32 module_index);
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void nx_dpc_set_sync_lcdtype(u32 module_index, int stnlcd,
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int dual_view_enb, int bit_widh,
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u8 cpcycle);
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void nx_dpc_set_up_scale_control(u32 module_index, int up_scale_enb,
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int filter_enb, u32 hscale,
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u16 source_width);
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void nx_dpc_set_mputime(u32 module_index, u8 setup, u8 hold, u8 acc);
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void nx_dpc_set_index(u32 module_index, u32 index);
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void nx_dpc_set_data(u32 module_index, u32 data);
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void nx_dpc_set_cmd_buffer_flush(u32 module_index);
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void nx_dpc_set_cmd_buffer_clear(u32 module_index);
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void nx_dpc_set_cmd_buffer_write(u32 module_index, u32 cmd_data);
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void nx_dpc_set(u32 module_index);
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u32 nx_dpc_get_data(u32 module_index);
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u32 nx_dpc_get_status(u32 module_index);
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void nx_dpc_rgbmask(u32 module_index, u32 rgbmask);
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void nx_dpc_set_pad_location(u32 module_index, u32 index, u32 regvalue);
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u32 nx_dpc_get_field_flag(u32 module_index);
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void nx_dpc_set_sync_v(u32 module_index, u32 avheight, u32 vsw, u32 vfp,
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|
u32 vbp);
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int nx_dpc_init_reg_test(u32 module_index);
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void nx_dpc_set_encoder_control_reg(u32 module_index, u32 param_a,
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u32 param_b, u32 param_c);
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void nx_dpc_set_encoder_shcphase_control(u32 module_index,
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|
u32 chroma_param);
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void nx_dpc_set_encoder_timing_config_reg(u32 module_index, u32 inctl);
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void nx_dpc_set_encoder_dacoutput_select(u32 module_index, u8 dacsel0,
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u8 dacsel1, u8 dacsel2,
|
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|
u8 dacsel3, u8 dacsel4,
|
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|
u8 dacsel5);
|
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|
void nx_dpc_set_encoder_sync_location(u32 module_index, u16 hsoe,
|
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|
u16 hsob, u16 vsob, u16 vsoe,
|
||
|
u8 vsost, int novrst);
|
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|
void nx_dpc_set_encoder_dacpower_enable(u32 module_index, u8 dacpd);
|
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|
void nx_dpc_set_ycorder(u32 module_index, enum nx_dpc_ycorder ycorder);
|
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|
void nx_dpc_set_luma_gain(u32 module_index, u32 luma_gain);
|
||
|
|
||
|
void nx_dpc_set_secondary_dpcsync(u32 module_index, int benb);
|
||
|
int nx_dpc_get_secondary_dpcsync(u32 module_index);
|
||
|
void nx_dpc_set_encenable(u32 module_index, int benb);
|
||
|
int nx_dpc_get_encenable(u32 module_index);
|
||
|
void nx_dpc_set_video_encoder_power_down(u32 module_index, int benb);
|
||
|
int nx_dpc_get_video_encoder_power_down(u32 module_index);
|
||
|
void nx_dpc_set_video_encoder_mode(u32 module_index, enum nx_dpc_vbs vbs,
|
||
|
int bpedestal);
|
||
|
void nx_dpc_set_video_encoder_schlock_control(u32 module_index,
|
||
|
int bfreerun);
|
||
|
int nx_dpc_get_video_encoder_schlock_control(u32 module_index);
|
||
|
void nx_dpc_set_video_encoder_bandwidth(u32 module_index,
|
||
|
enum nx_dpc_bandwidth luma,
|
||
|
enum nx_dpc_bandwidth chroma);
|
||
|
void nx_dpc_get_video_encoder_bandwidth(u32 module_index,
|
||
|
enum nx_dpc_bandwidth *pluma,
|
||
|
enum nx_dpc_bandwidth *pchroma);
|
||
|
void nx_dpc_set_video_encoder_color_control(u32 module_index, s8 sch,
|
||
|
s8 hue, s8 sat,
|
||
|
s8 crt, s8 brt);
|
||
|
void nx_dpc_get_video_encoder_color_control(u32 module_index,
|
||
|
s8 *psch, s8 *phue,
|
||
|
s8 *psat, s8 *pcrt,
|
||
|
s8 *pbrt);
|
||
|
void nx_dpc_set_video_encoder_fscadjust(u32 module_index,
|
||
|
int16_t adjust);
|
||
|
u16 nx_dpc_get_video_encoder_fscadjust(u32 module_index);
|
||
|
void nx_dpc_set_video_encoder_timing(u32 module_index, u32 hsos,
|
||
|
u32 hsoe, u32 vsos, u32 vsoe);
|
||
|
void nx_dpc_get_video_encoder_timing(u32 module_index, u32 *phsos,
|
||
|
u32 *phsoe, u32 *pvsos,
|
||
|
u32 *pvsoe);
|
||
|
void nx_dpc_set_sync_v(u32 module_index, u32 avheight, u32 vsw, u32 vfp,
|
||
|
u32 vbp);
|
||
|
|
||
|
int nx_dpc_init_reg_test(u32 module_index);
|
||
|
void nx_dpc_set_encoder_control_reg(u32 module_index, u32 param_a,
|
||
|
u32 param_b, u32 param_c);
|
||
|
void nx_dpc_set_encoder_shcphase_control(u32 module_index,
|
||
|
u32 chroma_param);
|
||
|
void nx_dpc_set_encoder_timing_config_reg(u32 module_index, u32 inctl);
|
||
|
void nx_dpc_set_encoder_dacoutput_select(u32 module_index, u8 dacsel0,
|
||
|
u8 dacsel1, u8 dacsel2,
|
||
|
u8 dacsel3, u8 dacsel4,
|
||
|
u8 dacsel5);
|
||
|
void nx_dpc_set_encoder_sync_location(u32 module_index, u16 hsoe,
|
||
|
u16 hsob, u16 vsob, u16 vsoe,
|
||
|
u8 vsost, int novrst);
|
||
|
void nx_dpc_set_encoder_dacpower_enable(u32 module_index, u8 dacpd);
|
||
|
void nx_dpc_set_ycorder(u32 module_index, enum nx_dpc_ycorder ycorder);
|
||
|
void nx_dpc_set_luma_gain(u32 module_index, u32 luma_gain);
|
||
|
|
||
|
#endif
|