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u-boot/drivers/pci/Kconfig

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drivers/pci/Kconfig: Add PCI Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-26 21:15:37 +00:00
menuconfig PCI
bool "PCI support"
pci: Require DM_PCI As the migration deadline has passed, require that DM_PCI be used. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-15 01:34:32 +00:00
depends on DM
x86: kconfig: Select PCI and DM_PCI PCI is the de facto interconnect bus in an x86 system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:09 +00:00
default y if PPC
drivers/pci/Kconfig: Add PCI Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-26 21:15:37 +00:00
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
peripherals.
pci: Drop DM_PCI This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 00:54:44 +00:00
This subsystem requires driver model.
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:25 +00:00
pci: Require DM_PCI As the migration deadline has passed, require that DM_PCI be used. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-15 01:34:32 +00:00
if PCI
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-27 02:51:30 +00:00
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
help
Enable compatibility functions for PCI so that old code can be used
pci: Drop DM_PCI This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 00:54:44 +00:00
with CONFIG_PCI enabled. This should be used as an interim
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-27 02:51:30 +00:00
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
Convert CONFIG_SYS_PCI_64BIT to Kconfig This converts the following to Kconfig: CONFIG_SYS_PCI_64BIT Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-13 03:12:32 +00:00
config SYS_PCI_64BIT
bool "Enable 64-bit PCI resources"
default y if PPC
help
Enable 64-bit PCI resource access.
arm64: a37xx: pci: add support for aardvark pcie driver This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-26 07:57:29 +00:00
config PCI_AARDVARK
bool "Enable Aardvark PCIe driver"
arm64: a37xx: pci: Depends on DM_GPIO For proper initialization of aardvark pci driver it is required to de-assert reset GPIO. So depeneds on DM_GPIO option. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-25 08:45:04 +00:00
depends on DM_GPIO
arm64: a37xx: pci: add support for aardvark pcie driver This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-26 07:57:29 +00:00
depends on ARMADA_3700
help
Say Y here if you want to enable PCIe controller support on
Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
Aardvark hardware.
pci: Move CONFIG_PCI_PNP to Kconfig Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-10-17 06:35:18 +00:00
config PCI_PNP
bool "Enable Plug & Play support for PCI"
default y
help
Enable PCI memory and I/O space resource allocation and assignment.
pci: pci-uclass: Add multi entry support for memory regions Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-10-20 00:10:20 +00:00
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
help
Enable PCI memory regions to be of multiple entry. Multiple entry
here refers to allow more than one count of address ranges for MEMORY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
dm: pci: add option to map virtual system memory base address On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE is still used as a virtual, CPU-mapped address instead of being used as physical address. Converting all MIPS boards and generic MIPS code to fix that is not trivial. Due to the approaching deadline for PCI DM conversion, this workaround is required for MIPS boards with PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved. Add a compile-time option to let the PCI uclass core optionally map the DRAM address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-15 18:53:56 +00:00
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on MIPS
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
being used as virtual address.
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-10-19 23:07:20 +00:00
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
help
Say Y here if you want to enable PCI Single Root I/O Virtualization
capability support. This helps to enumerate Virtual Function devices
if available on a PCI Physical Function device and probe for
applicable drivers.
pci: Add config for Enhanced Allocation Add a config to control whether Enhanced Allocation is supported by the driver. Signed-off-by: Andrew Scull <ascull@google.com>
2022-04-21 16:11:16 +00:00
config PCI_ENHANCED_ALLOCATION
bool "Enable support for Enhanced Allocation of resources"
default y
help
Enable support for Enhanced Allocation which can be used by supported
devices in place of traditional BARS for allocation of resources.
pci: pci-uclass: Add support for Alternate-RoutingID capability If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-10-24 01:40:36 +00:00
config PCI_ARID
bool "Enable Alternate Routing-ID support for PCI"
help
Say Y here if you want to enable Alternate Routing-ID capability
support on PCI devices. This helps to skip some devices in BDF
scan that are not present.
PCI: Add driver for a 'pci-host-ecam-generic' host controller QEMU emulates such a device with '-machine virt,highmem=off' on ARM. The 'highmem=off' part is required for things to work as the PCI code in U-Boot doesn't seem to support 64-bit BARs. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-19 20:18:06 +00:00
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
help
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
pci: synquacer: Add SynQuacer ECAM based PCIe driver Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:44:06 +00:00
config PCIE_ECAM_SYNQUACER
bool "SynQuacer ECAM-based PCI host controller support"
select PCI_INIT_R
select PCI_REGION_MULTI_ENTRY
help
Say Y here if you want to enable support for Socionext
SynQuacer SoC's ECAM-based PCIe host controllers.
Note that this must be configured when boot because Linux driver
expects the PCIe RC has been configured in the bootloader.
arm: add initial support for the Phytium Durian Board This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-10-31 07:51:08 +00:00
config PCI_PHYTIUM
bool "Phytium PCIe support"
help
Say Y here if you want to enable PCIe controller support on
Phytium SoCs.
pci: mvebu: Add PCIe driver for Armada-8K This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
2016-10-27 11:29:41 +00:00
config PCIE_DW_MVEBU
bool "Enable Armada-8K PCIe driver (DesignWare core)"
depends on ARMADA_8K
help
Say Y here if you want to enable PCIe controller support on
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
DesignWare hardware.
drivers: pci: add pcie support for fu740 Add pcie driver for SiFive fu740, the driver depends on fu740 gpio, clk and reset driver to do init. Force running at Gen1 for better capatible enumeration. Several devices are tested: a) M.2 NVMe SSD b) USB-to-PCI adapter c) Ethernet adapter (E1000 compatible) Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-27 13:52:10 +00:00
config PCIE_DW_SIFIVE
bool "Enable SiFive FU740 PCIe"
depends on CLK_SIFIVE_PRCI
depends on RESET_SIFIVE
depends on SIFIVE_GPIO
select PCIE_DW_COMMON
help
Say Y here if you want to enable PCIe controller support on
FU740.
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-24 14:33:02 +00:00
config PCIE_FSL
bool "FSL PowerPC PCIe support"
help
Say Y here if you want to enable PCIe controller support on FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
pci: add DM based mpc85xx driver add DM based PCI Configuration space access support for MPC85xx PCI Bridge. This driver is based on arch/powerpc/cpu/mpc85xx/pci.c In the old driver there is a fix for a hw issue on the TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I have no such hardware I did not port this part. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-14 09:29:39 +00:00
config PCI_MPC85XX
bool "MPC85XX PowerPC PCI support"
help
Say Y here if you want to enable PCI controller support on FSL
PowerPC MPC85xx SoC.
pci: rmobile: Add RCar Gen2 PCIe controller driver Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as access the on-SoC USB EHCI controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-18 13:35:35 +00:00
config PCI_RCAR_GEN2
bool "Renesas RCar Gen2 PCIe driver"
depends on RCAR_32
help
Say Y here if you want to enable PCIe controller support on
Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
also used to access EHCI USB controller on the SoC.
pci: renesas: Add RCar Gen3 PCIe controller driver Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-16 10:49:19 +00:00
config PCI_RCAR_GEN3
bool "Renesas RCar Gen3 PCIe driver"
depends on RCAR_GEN3
help
Say Y here if you want to enable PCIe controller support on
Renesas RCar Gen3 SoCs.
dm: sandbox: Add a simple PCI driver Add a driver which can access emulations of devices and make them available in sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:27 +00:00
config PCI_SANDBOX
bool "Sandbox PCI support"
pci: Drop DM_PCI This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 00:54:44 +00:00
depends on SANDBOX
dm: sandbox: Add a simple PCI driver Add a driver which can access emulations of devices and make them available in sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:27 +00:00
help
Support PCI on sandbox, as an emulated bus. This permits testing of
PCI feature such as bus scanning, device configuration and device
access. The available (emulated) devices are defined statically in
the device tree but the normal PCI scan technique is used to find
then.
dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
2015-11-20 03:26:55 +00:00
config PCI_TEGRA
bool "Tegra PCI support"
rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRA Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-06 12:02:41 +00:00
depends on ARCH_TEGRA
pci: tegra: port to standard clock/reset/pwr domain APIs Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-05 22:10:34 +00:00
depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
2015-11-20 03:26:55 +00:00
help
Enable support for the PCIe controller found on some generations of
Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
with a total of 5 lanes. Some boards require this for Ethernet
support to work (e.g. beaver, jetson-tk1).
pci: Add PCI controller driver for OcteonTX / TX2 Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-10-20 00:28:01 +00:00
config PCI_OCTEONTX
bool "OcteonTX PCI support"
depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2)
help
Enable support for the OcteonTX/TX2 SoC family ECAM/PEM controllers.
These controllers provide PCI configuration access to all on-board
peripherals so it should only be disabled for testing purposes
mips: octeon: Add Octeon PCIe host controller driver This patch adds the PCIe host controller driver for MIPS Octeon II/III. The driver mainly consist of the PCI config functions, as all of the complex serdes related port / lane setup, is done in the serdes / pcie code available in the "arch/mips/mach-octeon" directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-07 06:43:35 +00:00
config PCIE_OCTEON
bool "MIPS Octeon PCIe support"
depends on ARCH_OCTEON
help
Enable support for the MIPS Octeon SoC family PCIe controllers.
pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-08 06:47:31 +00:00
config PCI_XILINX
bool "Xilinx AXI Bridge for PCI Express"
help
Enable support for the Xilinx AXI bridge for PCI express, an IP block
which can be used on some generations of Xilinx FPGAs.
pci: layerscape: add pci driver based on DM There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-13 06:54:17 +00:00
config PCIE_LAYERSCAPE
pci: layerscape: Add specific config entry for RC and EP mode driver Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-09 15:31:42 +00:00
bool
config PCIE_LAYERSCAPE_RC
bool "Layerscape PCIe Root Complex mode support"
select PCIE_LAYERSCAPE
help
Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
SoC may have one or several PCIe controllers. Each controller can be
configured to Root Complex mode by clearing the corresponding bit of
RCW[HOST_AGT_PEX].
pci: layerscape: add a way of specifying additional iommu mappings In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-10 09:42:19 +00:00
config PCI_IOMMU_EXTRA_MAPPINGS
bool "Support for specifying extra IOMMU mappings for PCI"
depends on PCIE_LAYERSCAPE_RC
help
Enable support for specifying extra IOMMU mappings for PCI
controllers through a special env var called "pci_iommu_extra" or
through a device tree property named "pci-iommu-extra" placed in
the node describing the PCI controller.
The intent is to cover SR-IOV scenarios which need mappings for VFs
and PCI hot-plug scenarios. More documentation can be found under:
arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra
pci: layerscape: Add specific config entry for RC and EP mode driver Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-09 15:31:42 +00:00
config PCIE_LAYERSCAPE_EP
bool "Layerscape PCIe Endpoint mode support"
select PCIE_LAYERSCAPE
select PCI_ENDPOINT
pci: layerscape: add pci driver based on DM There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-13 06:54:17 +00:00
help
pci: layerscape: Add specific config entry for RC and EP mode driver Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-09 15:31:42 +00:00
Enable Layerscape PCIe Endpoint mode driver support. The Layerscape
SoC may have one or several PCIe controllers. Each controller can be
configured to Endpoint mode by setting the corresponding bit of
RCW[HOST_AGT_PEX].
pci: layerscape: add pci driver based on DM There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-13 06:54:17 +00:00
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-08 10:15:46 +00:00
config PCIE_LAYERSCAPE_GEN4
bool "Layerscape Gen4 PCIe support"
help
Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
several PCIe controllers. The PCIe controller can work in RC or
EP mode according to RCW[HOST_AGT_PEX] setting.
pci: layerscape: move PCIE related CONFIG to PCI Kconfig move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-30 13:14:00 +00:00
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
pci: layerscape: Add specific config entry for RC and EP mode driver Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-09 15:31:42 +00:00
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
pci: layerscape: move PCIE related CONFIG to PCI Kconfig move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-30 13:14:00 +00:00
default "fsl,ls1012a-pcie" if ARCH_LS1012A
default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
pci: layerscape: update the searching compatible of LX2160A PCIe The current fixup of LX2160A PCIe nodes is based on non-production rev1 silicon, and in Linux the nodes have been updated for rev2 silicon, so update the searching compatible string to match the kernel changes. And for compatibility with the rev1 nodes, move forward the board specific fixup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-12-07 10:13:12 +00:00
default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A
pci: layerscape: move PCIE related CONFIG to PCI Kconfig move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-30 13:14:00 +00:00
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
pci: layerscape: Manage PCIe EP compatible string via Kconfig The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-30 13:14:10 +00:00
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
pci: layerscape: Add specific config entry for RC and EP mode driver Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-09 15:31:42 +00:00
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
pci: layerscape: Manage PCIe EP compatible string via Kconfig The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-30 13:14:10 +00:00
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT
to complete fixup.
Convert CONFIG_PCIE_IMX to Kconfig This converts the following to Kconfig: CONFIG_PCIE_IMX Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-20 12:07:46 +00:00
config PCIE_IMX
bool "i.MX PCIe support"
depends on ARCH_MX6
pci: intel: Add Intel FPGA PCIe controller driver Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested with the Intel e1000e NIC driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-04-20 13:55:45 +00:00
config PCIE_INTEL_FPGA
bool "Intel FPGA PCIe support"
help
Say Y here if you want to enable PCIe controller support on Intel
FPGA, example Stratix 10.
drivers: pcie: add Broadcom IPROC PCIe RC driver Add support for IPROC PAXC PCIe RC driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-12 07:59:50 +00:00
config PCIE_IPROC
bool "Iproc PCIe support"
help
Broadcom iProc PCIe controller driver.
Say Y here if you want to enable Broadcom iProc PCIe controller,
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-01-25 10:52:43 +00:00
config PCI_MVEBU
pci: pci_mvebu: Add support for Kirkwood PCIe controllers Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base address of PCIe mappings. Size of PCIe windows is not defined in any macro yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE macros. Kirkwood arch code already maps mbus windows for io and mem, so avoid calling mvebu_mbus_add_window_by_id() function which would try to do duplicate window mapping. Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible string, so mark pci_mvebu.c driver as compatible for it. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-13 13:28:04 +00:00
bool "Enable Kirkwood / Armada 370/XP/375/38x PCIe driver"
depends on (ARCH_KIRKWOOD || ARCH_MVEBU)
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-01-25 10:52:43 +00:00
select MISC
arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers") it is required to set Maximum Link Width bits of PCIe Root Port Link Capabilities Register depending of number of used serdes lanes. As this register is part of PCIe address space and not serdes address space, move it into pci_mvebu.c driver. Read number of PCIe lanes from DT property "num-lanes" which is used also by other PCIe controller drivers in Linux kernel. If this property is absent then it defaults to 1. This property needs to be set to 4 for every mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4. Enabling of PCIe port needs to be done afer all registers in PCIe address space are properly configure. For this purpose use new mvebu-reset driver (part of system-controller) and remove this code from serdes code. Because some PCIe ports cannot be enabled individually, it is required to first setup all PCIe ports and then enable them. This change contains also all required "num-lanes" and "resets" DTS properties, to make pci_mvebu.c driver work correctly. Signed-off-by: Pali Rohár <pali@kernel.org>
2021-12-21 11:20:19 +00:00
select DM_RESET
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-01-25 10:52:43 +00:00
help
Say Y here if you want to enable PCIe controller support on
pci: pci_mvebu: Add support for Kirkwood PCIe controllers Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base address of PCIe mappings. Size of PCIe windows is not defined in any macro yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE macros. Kirkwood arch code already maps mbus windows for io and mem, so avoid calling mvebu_mbus_add_window_by_id() function which would try to do duplicate window mapping. Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible string, so mark pci_mvebu.c driver as compatible for it. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-13 13:28:04 +00:00
Kirkwood and Armada 370/XP/375/38x SoCs.
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-01-25 10:52:43 +00:00
pci: add common Designware PCIe functions With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated. This introduce a "common" DW PCIe helpers file with common code merged from the dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson. The following changes will switch the dw_ti and dw_rockchip to use these helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Green Wan <green.wan@sifive.com> [bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-25 14:49:18 +00:00
config PCIE_DW_COMMON
bool
pcie: ti: add driver for AM65x PCIe RC Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-01 13:42:57 +00:00
config PCI_KEYSTONE
bool "TI Keystone PCIe controller"
pci: pcie_dw_ti: migrate to common Designware PCIe functions Migrate the dw_ti driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-03-25 14:49:19 +00:00
select PCIE_DW_COMMON
pcie: ti: add driver for AM65x PCIe RC Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-01 13:42:57 +00:00
help
Say Y here if you want to enable PCI controller support on AM654 SoC.
pci: mediatek: add PCIe controller support for MT7623 This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-08-22 10:26:49 +00:00
config PCIE_MEDIATEK
bool "MediaTek PCIe Gen2 controller"
depends on ARCH_MEDIATEK
help
Say Y here if you want to enable Gen2 PCIe controller,
which could be found on MT7623 SoC family.
pci: add Amlogic Meson Designware PCIe controller Add support for the DW PCIe controller found in the Amlogic Meson AXG and G12 (G12A, G12B, SM1) SoCs. This uses the common DW PCIe helpers introducted previously. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-03-25 14:49:21 +00:00
config PCIE_DW_MESON
bool "Amlogic Meson DesignWare based PCIe controller"
depends on ARCH_MESON
select PCIE_DW_COMMON
help
Say Y here if you want to enable DW PCIe controller support on
Amlogic SoCs.
pci: Add Rockchip PCIe controller driver Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-09 16:56:21 +00:00
config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"
pci: kconfig: Setup proper dependency for PCIE_ROCKCHIP There is missing dependency for PCIE_ROCKCHIP which selects PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP. WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE Depends on [n]: ARCH_ROCKCHIP [=n] Selected by [y]: - PCIE_ROCKCHIP [=y] && PCI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-19 08:44:15 +00:00
depends on ARCH_ROCKCHIP
pci: rockchip: Switch to generic-phy Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-09 18:11:02 +00:00
select PHY_ROCKCHIP_PCIE
pci: Add Rockchip PCIe controller driver Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-09 16:56:21 +00:00
default y if ROCKCHIP_RK3399
help
Say Y here if you want to enable PCIe controller support on
Rockchip SoCs.
pci: Add Rockchip dwc based PCIe controller driver Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-15 10:01:22 +00:00
config PCIE_DW_ROCKCHIP
bool "Rockchip DesignWare based PCIe controller"
depends on ARCH_ROCKCHIP
pci: pcie_dw_rockchip: migrate to common Designware PCIe functions Migrate the dw_rockchip driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-03-25 14:49:20 +00:00
select PCIE_DW_COMMON
pci: Add Rockchip dwc based PCIe controller driver Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-15 10:01:22 +00:00
select PHY_ROCKCHIP_SNPS_PCIE3
help
Say Y here if you want to enable DW PCIe controller support on
Rockchip SoCs.
pci: Add driver for Broadcom BCM2711 SoC PCIe controller This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-25 11:39:58 +00:00
config PCI_BRCMSTB
bool "Broadcom STB PCIe controller"
depends on ARCH_BCM283X
help
Say Y here if you want to enable support for PCIe controller
on Broadcom set-top-box (STB) SoCs.
This driver currently supports only BCM2711 SoC and RC mode
of the controller.
pci: uniphier: Add UniPhier PCIe controller driver Add PCIe driver for UniPhier SoCs. This PCIe controller is based on Synopsys DesignWare Core IP. This version doesn't apply common DW functions because supported controller doesn't have unroll version of iATU. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-06 10:01:09 +00:00
config PCIE_UNIPHIER
bool "Socionext UniPhier PCIe driver"
depends on ARCH_UNIPHIER
select PHY_UNIPHIER_PCIE
help
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
drivers/pci/Kconfig: Add PCI Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-26 21:15:37 +00:00
endif
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