2018-11-02 14:21:03 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: R5 MPU region definitions
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*
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* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/kernel.h>
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#include "common.h"
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struct mpu_region_config k3_mpu_regions[16] = {
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/*
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* Make all 4GB as Device Memory and not executable. We are overriding
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* it with next region for any requirement.
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*/
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{0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
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REGION_4GB},
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/* SPL code area marking it as WB and Write allocate. */
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{CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_8MB},
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/* U-Boot's code area marking it as WB and Write allocate */
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2022-11-16 18:10:37 +00:00
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{CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
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2018-11-02 14:21:03 +00:00
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O_I_WB_RD_WR_ALLOC, REGION_2GB},
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2020-02-12 08:25:05 +00:00
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/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
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{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
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REGION_8MB},
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2018-11-02 14:21:03 +00:00
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{0x0, 4, 0x0, 0x0, 0x0, 0x0},
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{0x0, 5, 0x0, 0x0, 0x0, 0x0},
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{0x0, 6, 0x0, 0x0, 0x0, 0x0},
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{0x0, 7, 0x0, 0x0, 0x0, 0x0},
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{0x0, 8, 0x0, 0x0, 0x0, 0x0},
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{0x0, 9, 0x0, 0x0, 0x0, 0x0},
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{0x0, 10, 0x0, 0x0, 0x0, 0x0},
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{0x0, 11, 0x0, 0x0, 0x0, 0x0},
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{0x0, 12, 0x0, 0x0, 0x0, 0x0},
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{0x0, 13, 0x0, 0x0, 0x0, 0x0},
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{0x0, 14, 0x0, 0x0, 0x0, 0x0},
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{0x0, 15, 0x0, 0x0, 0x0, 0x0},
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};
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void setup_k3_mpu_regions(void)
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{
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setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
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}
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