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u-boot/doc/device-tree-bindings/net/ti,dp83867.txt

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net: phy: dp83867: Add device tree bindings and documentation Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-02 20:45:58 +00:00
* Texas Instruments - dp83867 Giga bit ethernet phy
Required properties:
- reg - The ID number for the phy, usually a small integer
- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
for applicable values
net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device. One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux). Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-28 06:25:37 +00:00
- enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
net: phy: ti: Add binding for the CLK_OUT pin muxing The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin. Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for the CLK_OUT pin muxing option") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-28 06:25:39 +00:00
- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
for applicable values
net: phy: dp83867: Add device tree bindings and documentation Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-02 20:45:58 +00:00
Default child nodes are standard Ethernet PHY device
nodes as described in doc/devicetree/bindings/net/ethernet.txt
Example:
ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device. One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux). Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-28 06:25:37 +00:00
enet-phy-lane-no-swap;
net: phy: ti: Add binding for the CLK_OUT pin muxing The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin. Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for the CLK_OUT pin muxing option") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-28 06:25:39 +00:00
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
net: phy: dp83867: Add device tree bindings and documentation Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-02 20:45:58 +00:00
};
Datasheet can be found:
http://www.ti.com/product/DP83867IR/datasheet
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