mirror of
https://github.com/AsahiLinux/u-boot
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42 lines
1.3 KiB
Text
42 lines
1.3 KiB
Text
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*/
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/*
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* NOTE: The layout of the GNVS structure below must match the layout in
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* soc/intel/apollolake/include/soc/nvs.h !!!
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*
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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SCDP, 8, // 0x29 - SD_CD GPIO portid
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SCDO, 8, // 0x2A - GPIO pad offset relative to the community
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UIOR, 8, // 0x2B - UART debug controller init on S3 resume
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EPCS, 8, // 0x2C - SGX Enabled status
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EMNA, 64, // 0x2D - 0x34 EPC base address
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ELNG, 64, // 0x35 - 0x3C EPC Length
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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#include <asm/acpi/cros_gnvs.asl>
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}
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