2022-07-12 07:12:11 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm QCS404 sysmap
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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#ifndef _MACH_SYSMAP_QCS404_H
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#define _MACH_SYSMAP_QCS404_H
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#define GICD_BASE (0x0b000000)
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#define GICC_BASE (0x0b002000)
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x21000)
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2023-02-01 13:58:50 +00:00
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#define GPLL1_STATUS (0x20000)
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2022-07-12 07:12:11 +00:00
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#define APCS_GPLL_ENA_VOTE (0x45000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
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/* BLSP1 AHB clock (root clock for BLSP) */
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#define BLSP1_AHB_CBCR 0x1008
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/* Uart clock control registers */
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#define BLSP1_UART2_BCR (0x3028)
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#define BLSP1_UART2_APPS_CBCR (0x302C)
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#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
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#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
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#define BLSP1_UART2_APPS_M (0x303C)
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#define BLSP1_UART2_APPS_N (0x3040)
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#define BLSP1_UART2_APPS_D (0x3044)
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2023-02-13 04:49:09 +00:00
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/* I2C controller clock control registerss */
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#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
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#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
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#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
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#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
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#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
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#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
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#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
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#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
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#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
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#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
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#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
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#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
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#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
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#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
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#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
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2022-07-12 07:12:11 +00:00
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/* SD controller clock control registers */
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#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
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#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
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#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
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#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
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#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
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#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
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#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
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#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
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2022-08-04 14:27:15 +00:00
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/* USB-3.0 controller clock control registers */
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#define SYS_NOC_USB3_CBCR (0x26014)
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#define USB30_BCR (0x39000)
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#define USB3PHY_BCR (0x39008)
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#define USB30_MASTER_CBCR (0x3900C)
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#define USB30_SLEEP_CBCR (0x39010)
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#define USB30_MOCK_UTMI_CBCR (0x39014)
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#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
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#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
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#define USB30_MASTER_CMD_RCGR (0x39028)
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#define USB30_MASTER_CFG_RCGR (0x3902C)
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#define USB30_MASTER_M (0x39030)
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#define USB30_MASTER_N (0x39034)
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#define USB30_MASTER_D (0x39038)
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#define USB2A_PHY_SLEEP_CBCR (0x4102C)
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#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
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2023-02-01 13:58:50 +00:00
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/* ETH controller clock control registers */
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#define ETH_PTP_CBCR (0x4e004)
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#define ETH_RGMII_CBCR (0x4e008)
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#define ETH_SLAVE_AHB_CBCR (0x4e00c)
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#define ETH_AXI_CBCR (0x4e010)
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#define EMAC_PTP_CMD_RCGR (0x4e014)
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#define EMAC_PTP_CFG_RCGR (0x4e018)
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#define EMAC_CMD_RCGR (0x4e01c)
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#define EMAC_CFG_RCGR (0x4e020)
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#define EMAC_M (0x4e024)
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#define EMAC_N (0x4e028)
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#define EMAC_D (0x4e02c)
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2022-07-12 07:12:11 +00:00
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#endif
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