mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
546 lines
16 KiB
C
546 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#include <config.h>
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/tieoff.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/display.h>
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#include <linux/delay.h>
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#include "soc/s5pxx18_soc_dpc.h"
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#include "soc/s5pxx18_soc_hdmi.h"
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#include "soc/s5pxx18_soc_disptop.h"
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#include "soc/s5pxx18_soc_disptop_clk.h"
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#define __io_address(a) (void *)(uintptr_t)(a)
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static const u8 hdmiphy_preset74_25[32] = {
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0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0xc8, 0x81,
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0xe8, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0a,
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0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x86, 0x54,
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0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x10, 0x80,
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};
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static const u8 hdmiphy_preset148_5[32] = {
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0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0xc8, 0x81,
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0xe8, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0a,
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0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x86, 0x54,
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0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
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};
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#define HDMIPHY_PRESET_TABLE_SIZE (32)
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enum NXP_HDMI_PRESET {
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NXP_HDMI_PRESET_720P = 0, /* 1280 x 720 */
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NXP_HDMI_PRESET_1080P, /* 1920 x 1080 */
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NXP_HDMI_PRESET_MAX
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};
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static void hdmi_reset(void)
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{
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nx_rstcon_setrst(RESET_ID_HDMI_VIDEO, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_HDMI_SPDIF, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_HDMI_TMDS, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_HDMI_VIDEO, RSTCON_NEGATE);
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nx_rstcon_setrst(RESET_ID_HDMI_SPDIF, RSTCON_NEGATE);
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nx_rstcon_setrst(RESET_ID_HDMI_TMDS, RSTCON_NEGATE);
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}
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static int hdmi_phy_enable(int preset, int enable)
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{
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const u8 *table = NULL;
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int size = 0;
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u32 addr, i = 0;
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if (!enable)
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return 0;
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switch (preset) {
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case NXP_HDMI_PRESET_720P:
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table = hdmiphy_preset74_25;
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size = 32;
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break;
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case NXP_HDMI_PRESET_1080P:
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table = hdmiphy_preset148_5;
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size = 31;
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break;
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default:
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printf("hdmi: phy not support preset %d\n", preset);
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return -EINVAL;
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}
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, (0 << 7));
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, (0 << 7));
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nx_hdmi_set_reg(0, HDMI_PHY_REG04, (0 << 4));
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nx_hdmi_set_reg(0, HDMI_PHY_REG04, (0 << 4));
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nx_hdmi_set_reg(0, HDMI_PHY_REG24, (1 << 7));
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nx_hdmi_set_reg(0, HDMI_PHY_REG24, (1 << 7));
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for (i = 0, addr = HDMI_PHY_REG04; size > i; i++, addr += 4) {
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nx_hdmi_set_reg(0, addr, table[i]);
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nx_hdmi_set_reg(0, addr, table[i]);
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}
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, 0x80);
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, 0x80);
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, (1 << 7));
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nx_hdmi_set_reg(0, HDMI_PHY_REG7C, (1 << 7));
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debug("%s: preset = %d\n", __func__, preset);
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return 0;
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}
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static inline int hdmi_wait_phy_ready(void)
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{
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int count = 500;
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do {
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u32 val = nx_hdmi_get_reg(0, HDMI_LINK_PHY_STATUS_0);
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if (val & 0x01) {
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printf("HDMI: phy ready...\n");
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return 1;
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}
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mdelay(10);
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} while (count--);
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return 0;
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}
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static inline int hdmi_get_vsync(int preset,
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struct dp_sync_info *sync,
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struct dp_ctrl_info *ctrl)
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{
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switch (preset) {
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case NXP_HDMI_PRESET_720P: /* 720p: 1280x720 */
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sync->h_active_len = 1280;
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sync->h_sync_width = 40;
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sync->h_back_porch = 220;
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sync->h_front_porch = 110;
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sync->h_sync_invert = 0;
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sync->v_active_len = 720;
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sync->v_sync_width = 5;
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sync->v_back_porch = 20;
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sync->v_front_porch = 5;
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sync->v_sync_invert = 0;
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break;
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case NXP_HDMI_PRESET_1080P: /* 1080p: 1920x1080 */
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sync->h_active_len = 1920;
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sync->h_sync_width = 44;
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sync->h_back_porch = 148;
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sync->h_front_porch = 88;
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sync->h_sync_invert = 0;
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sync->v_active_len = 1080;
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sync->v_sync_width = 5;
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sync->v_back_porch = 36;
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sync->v_front_porch = 4;
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sync->v_sync_invert = 0;
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break;
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default:
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printf("HDMI: not support preset sync %d\n", preset);
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return -EINVAL;
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}
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ctrl->clk_src_lv0 = 4;
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ctrl->clk_div_lv0 = 1;
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ctrl->clk_src_lv1 = 7;
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ctrl->clk_div_lv1 = 1;
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ctrl->out_format = outputformat_rgb888;
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ctrl->delay_mask = (DP_SYNC_DELAY_RGB_PVD | DP_SYNC_DELAY_HSYNC_CP1 |
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DP_SYNC_DELAY_VSYNC_FRAM | DP_SYNC_DELAY_DE_CP);
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ctrl->d_rgb_pvd = 0;
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ctrl->d_hsync_cp1 = 0;
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ctrl->d_vsync_fram = 0;
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ctrl->d_de_cp2 = 7;
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/* HFP + HSW + HBP + AVWidth-VSCLRPIXEL- 1; */
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ctrl->vs_start_offset = (sync->h_front_porch + sync->h_sync_width +
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sync->h_back_porch + sync->h_active_len - 1);
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ctrl->vs_end_offset = 0;
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/* HFP + HSW + HBP + AVWidth-EVENVSCLRPIXEL- 1 */
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ctrl->ev_start_offset = (sync->h_front_porch + sync->h_sync_width +
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sync->h_back_porch + sync->h_active_len - 1);
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ctrl->ev_end_offset = 0;
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debug("%s: preset: %d\n", __func__, preset);
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return 0;
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}
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static void hdmi_clock(void)
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{
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void *base =
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__io_address(nx_disp_top_clkgen_get_physical_address
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(to_mipi_clkgen));
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nx_disp_top_clkgen_set_base_address(to_mipi_clkgen, base);
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nx_disp_top_clkgen_set_clock_divisor_enable(to_mipi_clkgen, 0);
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nx_disp_top_clkgen_set_clock_pclk_mode(to_mipi_clkgen,
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nx_pclkmode_always);
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nx_disp_top_clkgen_set_clock_source(to_mipi_clkgen, HDMI_SPDIF_CLKOUT,
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2);
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nx_disp_top_clkgen_set_clock_divisor(to_mipi_clkgen, HDMI_SPDIF_CLKOUT,
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2);
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nx_disp_top_clkgen_set_clock_source(to_mipi_clkgen, 1, 7);
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nx_disp_top_clkgen_set_clock_divisor_enable(to_mipi_clkgen, 1);
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/* must initialize this !!! */
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nx_disp_top_hdmi_set_vsync_hsstart_end(0, 0);
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nx_disp_top_hdmi_set_vsync_start(0);
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nx_disp_top_hdmi_set_hactive_start(0);
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nx_disp_top_hdmi_set_hactive_end(0);
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}
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static void hdmi_vsync(struct dp_sync_info *sync)
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{
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int width = sync->h_active_len;
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int hsw = sync->h_sync_width;
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int hbp = sync->h_back_porch;
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int height = sync->v_active_len;
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int vsw = sync->v_sync_width;
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int vbp = sync->v_back_porch;
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int v_sync_s = vsw + vbp + height - 1;
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int h_active_s = hsw + hbp;
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int h_active_e = width + hsw + hbp;
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int v_sync_hs_se0 = hsw + hbp + 1;
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int v_sync_hs_se1 = hsw + hbp + 2;
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nx_disp_top_hdmi_set_vsync_start(v_sync_s);
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nx_disp_top_hdmi_set_hactive_start(h_active_s);
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nx_disp_top_hdmi_set_hactive_end(h_active_e);
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nx_disp_top_hdmi_set_vsync_hsstart_end(v_sync_hs_se0, v_sync_hs_se1);
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}
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static int hdmi_prepare(struct dp_sync_info *sync)
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{
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int width = sync->h_active_len;
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int hsw = sync->h_sync_width;
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int hfp = sync->h_front_porch;
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int hbp = sync->h_back_porch;
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int height = sync->v_active_len;
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int vsw = sync->v_sync_width;
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int vfp = sync->v_front_porch;
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int vbp = sync->v_back_porch;
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u32 h_blank, h_line, h_sync_start, h_sync_end;
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u32 v_blank, v2_blank, v_line;
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u32 v_sync_line_bef_1, v_sync_line_bef_2;
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u32 fixed_ffff = 0xffff;
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/* calculate sync variables */
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h_blank = hfp + hsw + hbp;
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v_blank = vfp + vsw + vbp;
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v2_blank = height + vfp + vsw + vbp;
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v_line = height + vfp + vsw + vbp; /* total v */
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h_line = width + hfp + hsw + hbp; /* total h */
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h_sync_start = hfp;
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h_sync_end = hfp + hsw;
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v_sync_line_bef_1 = vfp;
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v_sync_line_bef_2 = vfp + vsw;
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/* no blue screen mode, encoding order as it is */
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nx_hdmi_set_reg(0, HDMI_LINK_HDMI_CON_0, (0 << 5) | (1 << 4));
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/* set HDMI_LINK_BLUE_SCREEN_* to 0x0 */
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_R_0, 0x5555);
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_R_1, 0x5555);
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_G_0, 0x5555);
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_G_1, 0x5555);
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_B_0, 0x5555);
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nx_hdmi_set_reg(0, HDMI_LINK_BLUE_SCREEN_B_1, 0x5555);
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/* set HDMI_CON_1 to 0x0 */
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nx_hdmi_set_reg(0, HDMI_LINK_HDMI_CON_1, 0x0);
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nx_hdmi_set_reg(0, HDMI_LINK_HDMI_CON_2, 0x0);
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/* set interrupt : enable hpd_plug, hpd_unplug */
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nx_hdmi_set_reg(0, HDMI_LINK_INTC_CON_0,
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(1 << 6) | (1 << 3) | (1 << 2));
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/* set STATUS_EN to 0x17 */
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nx_hdmi_set_reg(0, HDMI_LINK_STATUS_EN, 0x17);
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/* TODO set HDP to 0x0 : later check hpd */
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nx_hdmi_set_reg(0, HDMI_LINK_HPD, 0x0);
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/* set MODE_SEL to 0x02 */
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nx_hdmi_set_reg(0, HDMI_LINK_MODE_SEL, 0x2);
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/* set H_BLANK_*, V1_BLANK_*, V2_BLANK_*, V_LINE_*,
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* H_LINE_*, H_SYNC_START_*, H_SYNC_END_ *
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* V_SYNC_LINE_BEF_1_*, V_SYNC_LINE_BEF_2_*
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*/
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nx_hdmi_set_reg(0, HDMI_LINK_H_BLANK_0, h_blank % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_H_BLANK_1, h_blank >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V1_BLANK_0, v_blank % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V1_BLANK_1, v_blank >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V2_BLANK_0, v2_blank % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V2_BLANK_1, v2_blank >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_LINE_0, v_line % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_LINE_1, v_line >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_H_LINE_0, h_line % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_H_LINE_1, h_line >> 8);
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if (width == 1280) {
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nx_hdmi_set_reg(0, HDMI_LINK_HSYNC_POL, 0x1);
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nx_hdmi_set_reg(0, HDMI_LINK_VSYNC_POL, 0x1);
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} else {
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nx_hdmi_set_reg(0, HDMI_LINK_HSYNC_POL, 0x0);
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nx_hdmi_set_reg(0, HDMI_LINK_VSYNC_POL, 0x0);
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}
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nx_hdmi_set_reg(0, HDMI_LINK_INT_PRO_MODE, 0x0);
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nx_hdmi_set_reg(0, HDMI_LINK_H_SYNC_START_0, (h_sync_start % 256) - 2);
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nx_hdmi_set_reg(0, HDMI_LINK_H_SYNC_START_1, h_sync_start >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_H_SYNC_END_0, (h_sync_end % 256) - 2);
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nx_hdmi_set_reg(0, HDMI_LINK_H_SYNC_END_1, h_sync_end >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_BEF_1_0,
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v_sync_line_bef_1 % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_BEF_1_1,
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v_sync_line_bef_1 >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_BEF_2_0,
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v_sync_line_bef_2 % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_BEF_2_1,
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v_sync_line_bef_2 >> 8);
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/* Set V_SYNC_LINE_AFT*, V_SYNC_LINE_AFT_PXL*, VACT_SPACE* */
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_1_0, fixed_ffff % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_1_1, fixed_ffff >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_2_0, fixed_ffff % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_2_1, fixed_ffff >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_3_0, fixed_ffff % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_3_1, fixed_ffff >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_4_0, fixed_ffff % 256);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_4_1, fixed_ffff >> 8);
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nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_5_0, fixed_ffff % 256);
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||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_5_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_6_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_6_1, fixed_ffff >> 8);
|
||
|
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_1_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_1_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_2_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_2_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_3_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_3_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_4_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_4_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_5_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_5_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_6_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_V_SYNC_LINE_AFT_PXL_6_1, fixed_ffff >> 8);
|
||
|
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE1_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE1_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE2_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE2_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE3_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE3_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE4_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE4_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE5_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE5_1, fixed_ffff >> 8);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE6_0, fixed_ffff % 256);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VACT_SPACE6_1, fixed_ffff >> 8);
|
||
|
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_CSC_MUX, 0x0);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SYNC_GEN_MUX, 0x0);
|
||
|
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SEND_START_0, 0xfd);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SEND_START_1, 0x01);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SEND_END_0, 0x0d);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SEND_END_1, 0x3a);
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_SEND_END_2, 0x08);
|
||
|
|
||
|
/* Set DC_CONTROL to 0x00 */
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_DC_CONTROL, 0x0);
|
||
|
|
||
|
if (IS_ENABLED(CONFIG_HDMI_PATTERN))
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VIDEO_PATTERN_GEN, 0x1);
|
||
|
else
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_VIDEO_PATTERN_GEN, 0x0);
|
||
|
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_GCP_CON, 0x0a);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void hdmi_init(void)
|
||
|
{
|
||
|
void *base;
|
||
|
/**
|
||
|
* [SEQ 2] set the HDMI CLKGEN's PCLKMODE to always enabled
|
||
|
*/
|
||
|
base =
|
||
|
__io_address(nx_disp_top_clkgen_get_physical_address(hdmi_clkgen));
|
||
|
nx_disp_top_clkgen_set_base_address(hdmi_clkgen, base);
|
||
|
nx_disp_top_clkgen_set_clock_pclk_mode(hdmi_clkgen, nx_pclkmode_always);
|
||
|
|
||
|
base = __io_address(nx_hdmi_get_physical_address(0));
|
||
|
nx_hdmi_set_base_address(0, base);
|
||
|
|
||
|
/**
|
||
|
* [SEQ 3] set the 0xC001100C[0] to 1
|
||
|
*/
|
||
|
nx_tieoff_set(NX_TIEOFF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL, 1);
|
||
|
|
||
|
/**
|
||
|
* [SEQ 4] release the resets of HDMI.i_PHY_nRST and HDMI.i_nRST
|
||
|
*/
|
||
|
nx_rstcon_setrst(RESET_ID_HDMI_PHY, RSTCON_ASSERT);
|
||
|
nx_rstcon_setrst(RESET_ID_HDMI, RSTCON_ASSERT);
|
||
|
nx_rstcon_setrst(RESET_ID_HDMI_PHY, RSTCON_NEGATE);
|
||
|
nx_rstcon_setrst(RESET_ID_HDMI, RSTCON_NEGATE);
|
||
|
}
|
||
|
|
||
|
void hdmi_enable(int input, int preset, struct dp_sync_info *sync, int enable)
|
||
|
{
|
||
|
if (enable) {
|
||
|
nx_hdmi_set_reg(0, HDMI_LINK_HDMI_CON_0,
|
||
|
(nx_hdmi_get_reg(0, HDMI_LINK_HDMI_CON_0) |
|
||
|
0x1));
|
||
|
hdmi_vsync(sync);
|
||
|
} else {
|
||
|
hdmi_phy_enable(preset, 0);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static int hdmi_setup(int input, int preset,
|
||
|
struct dp_sync_info *sync, struct dp_ctrl_info *ctrl)
|
||
|
{
|
||
|
u32 HDMI_SEL = 0;
|
||
|
int ret;
|
||
|
|
||
|
switch (input) {
|
||
|
case DP_DEVICE_DP0:
|
||
|
HDMI_SEL = primary_mlc;
|
||
|
break;
|
||
|
case DP_DEVICE_DP1:
|
||
|
HDMI_SEL = secondary_mlc;
|
||
|
break;
|
||
|
case DP_DEVICE_RESCONV:
|
||
|
HDMI_SEL = resolution_conv;
|
||
|
break;
|
||
|
default:
|
||
|
printf("HDMI: not support source device %d\n", input);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* [SEQ 5] set up the HDMI PHY to specific video clock.
|
||
|
*/
|
||
|
ret = hdmi_phy_enable(preset, 1);
|
||
|
if (ret < 0)
|
||
|
return ret;
|
||
|
|
||
|
/**
|
||
|
* [SEQ 6] I2S (or SPDIFTX) configuration for the source audio data
|
||
|
* this is done in another user app - ex> Android Audio HAL
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* [SEQ 7] Wait for ECID ready
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* [SEQ 8] release the resets of HDMI.i_VIDEO_nRST and HDMI.i_SPDIF_nRST
|
||
|
* and HDMI.i_TMDS_nRST
|
||
|
*/
|
||
|
hdmi_reset();
|
||
|
|
||
|
/**
|
||
|
* [SEQ 9] Wait for HDMI PHY ready (wait until 0xC0200020.[0], 1)
|
||
|
*/
|
||
|
if (hdmi_wait_phy_ready() == 0) {
|
||
|
printf("%s: failed to wait for hdmiphy ready\n", __func__);
|
||
|
hdmi_phy_enable(preset, 0);
|
||
|
return -EIO;
|
||
|
}
|
||
|
/* set mux */
|
||
|
nx_disp_top_set_hdmimux(1, HDMI_SEL);
|
||
|
|
||
|
/**
|
||
|
* [SEC 10] Set the DPC CLKGEN's Source Clock to HDMI_CLK &
|
||
|
* Set Sync Parameter
|
||
|
*/
|
||
|
hdmi_clock();
|
||
|
/* set hdmi link clk to clkgen vs default is hdmi phy clk */
|
||
|
|
||
|
/**
|
||
|
* [SEQ 11] Set up the HDMI Converter parameters
|
||
|
*/
|
||
|
hdmi_get_vsync(preset, sync, ctrl);
|
||
|
hdmi_prepare(sync);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void nx_hdmi_display(int module,
|
||
|
struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
|
||
|
struct dp_plane_top *top, struct dp_plane_info *planes,
|
||
|
struct dp_hdmi_dev *dev)
|
||
|
{
|
||
|
struct dp_plane_info *plane = planes;
|
||
|
int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1;
|
||
|
int count = top->plane_num;
|
||
|
int preset = dev->preset;
|
||
|
int i = 0;
|
||
|
|
||
|
debug("HDMI: display.%d\n", module);
|
||
|
|
||
|
switch (preset) {
|
||
|
case 0:
|
||
|
top->screen_width = 1280;
|
||
|
top->screen_height = 720;
|
||
|
sync->h_active_len = 1280;
|
||
|
sync->v_active_len = 720;
|
||
|
break;
|
||
|
case 1:
|
||
|
top->screen_width = 1920;
|
||
|
top->screen_height = 1080;
|
||
|
sync->h_active_len = 1920;
|
||
|
sync->v_active_len = 1080;
|
||
|
break;
|
||
|
default:
|
||
|
printf("hdmi not support preset %d\n", preset);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
printf("HDMI: display.%d, preset %d (%4d * %4d)\n",
|
||
|
module, preset, top->screen_width, top->screen_height);
|
||
|
|
||
|
dp_control_init(module);
|
||
|
dp_plane_init(module);
|
||
|
|
||
|
hdmi_init();
|
||
|
hdmi_setup(input, preset, sync, ctrl);
|
||
|
|
||
|
dp_plane_screen_setup(module, top);
|
||
|
for (i = 0; count > i; i++, plane++) {
|
||
|
if (!plane->enable)
|
||
|
continue;
|
||
|
dp_plane_layer_setup(module, plane);
|
||
|
dp_plane_layer_enable(module, plane, 1);
|
||
|
}
|
||
|
dp_plane_screen_enable(module, 1);
|
||
|
|
||
|
dp_control_setup(module, sync, ctrl);
|
||
|
dp_control_enable(module, 1);
|
||
|
|
||
|
hdmi_enable(input, preset, sync, 1);
|
||
|
}
|