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u-boot/arch/riscv/dts/ae350_32.dts

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riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "andestech,a25";
model = "andestech,a25";
aliases {
uart0 = &serial0;
spi0 = &spi;
};
chosen {
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <60000000>;
CPU0: cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
next-level-cache = <&L2>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
CPU1: cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
next-level-cache = <&L2>;
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
riscv: dts: Support four cores SMP Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:28 +00:00
CPU2: cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
next-level-cache = <&L2>;
CPU2_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU3: cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
next-level-cache = <&L2>;
CPU3_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
riscv: dts: move out AE350 L2 node from cpus node When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:10 +00:00
};
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
riscv: dts: move out AE350 L2 node from cpus node When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:10 +00:00
L2: l2-cache@e0500000 {
compatible = "v5l2cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0xe0500000 0x40000>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
/* The value format is <XRAMOCTL XRAMICTL> */
andes,tag-ram-ctl = <0 0>;
andes,data-ram-ctl = <0 0>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
compatible = "simple-bus";
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
ranges;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>;
riscv: dts: Support four cores SMP Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:28 +00:00
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
&CPU1_intc 11 &CPU1_intc 9
&CPU2_intc 11 &CPU2_intc 9
&CPU3_intc 11 &CPU3_intc 9>;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
};
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
#address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
riscv,ndev=<2>;
riscv: dts: Support four cores SMP Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:28 +00:00
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
};
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
plmt0@e6000000 {
compatible = "riscv,plmt0";
riscv: dts: Support four cores SMP Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:28 +00:00
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7
&CPU3_intc 7>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
reg = <0xe6000000 0x100000>;
};
};
spiclk: virt_100mhz {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0xf0400000 0x1000>;
clock-frequency = <60000000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
};
serial0: serial@f0300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0xf0300000 0x1000>;
interrupts = <9 4>;
clock-frequency = <19660800>;
reg-shift = <2>;
reg-offset = <32>;
no-loopback-test = <1>;
interrupt-parent = <&plic0>;
};
mac0: mac@e0100000 {
compatible = "andestech,atmac100";
reg = <0xe0100000 0x1000>;
interrupts = <19 4>;
interrupt-parent = <&plic0>;
};
mmc0: mmc@f0e00000 {
compatible = "andestech,atfsdc010";
max-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>;
fifo-depth = <0x10>;
reg = <0xf0e00000 0x1000>;
interrupts = <18 4>;
cap-sd-highspeed;
interrupt-parent = <&plic0>;
};
dma0: dma@f0c00000 {
compatible = "andestech,atcdmac300";
reg = <0xf0c00000 0x1000>;
interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
dma-channels = <8>;
interrupt-parent = <&plic0>;
};
lcd0: lcd@e0200000 {
compatible = "andestech,atflcdc100";
reg = <0xe0200000 0x1000>;
interrupts = <20 4>;
interrupt-parent = <&plic0>;
};
smc0: smc@e0400000 {
compatible = "andestech,atfsmc020";
reg = <0xe0400000 0x1000>;
};
snd0: snd@f0d00000 {
compatible = "andestech,atfac97";
reg = <0xf0d00000 0x1000>;
interrupts = <17 4>;
interrupt-parent = <&plic0>;
};
riscv: dts: ae350 support SMP Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:43 +00:00
pmu {
compatible = "riscv,base-pmu";
};
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
virtio_mmio@fe007000 {
interrupts = <0x17 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe007000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe006000 {
interrupts = <0x16 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe006000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe005000 {
interrupts = <0x15 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe005000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe004000 {
interrupts = <0x14 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe004000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe003000 {
interrupts = <0x13 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe003000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe002000 {
interrupts = <0x12 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe002000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe001000 {
interrupts = <0x11 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe001000 0x1000>;
compatible = "virtio,mmio";
};
virtio_mmio@fe000000 {
interrupts = <0x10 0x4>;
interrupt-parent = <0x2>;
reg = <0xfe000000 0x1000>;
compatible = "virtio,mmio";
};
nor@0,0 {
riscv: dts: Add #address-cells and #size-cells in nor node Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:29 +00:00
#address-cells = <1>;
#size-cells = <1>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
compatible = "cfi-flash";
riscv: dts: Add #address-cells and #size-cells in nor node Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-11-14 05:52:29 +00:00
reg = <0x88000000 0x4000000>;
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
bank-width = <2>;
device-width = <1>;
};
spi: spi@f0b00000 {
compatible = "andestech,atcspi200";
reg = <0xf0b00000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
clocks = <&spiclk>;
interrupts = <4 4>;
interrupt-parent = <&plic0>;
flash@0 {
dts: switch spi-flash to jedec, spi-nor compatible There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot dts files. This compatible has been added in sf_probe, let use it. This patch switches to jedec,spi-nor when spi-flash is used in the DTS and DTSI files, and removed spi-flash when jedec,spi-nor is already present. The x86 dts are switched in a separate commit since it depends on a change in fdtdec. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-10 10:16:20 +00:00
compatible = "jedec,spi-nor";
riscv: dts: Add ae350_32.dts for RV32I Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-13 08:33:29 +00:00
spi-max-frequency = <50000000>;
reg = <0>;
spi-cpol;
spi-cpha;
};
};
};
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