2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2008-07-11 19:10:13 +00:00
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/*
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* Power and Sleep Controller (PSC) functions.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2004 Texas Instruments.
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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2009-11-12 16:07:22 +00:00
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#include <asm/io.h>
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2008-07-11 19:10:13 +00:00
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/*
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2009-05-15 21:44:08 +00:00
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* The PSC manages three inputs to a "module" which may be a peripheral or
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* CPU. Those inputs are the module's: clock; reset signal; and sometimes
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* its power domain. For our purposes, we only care whether clock and power
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* are active, and the module is out of reset.
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*
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* DaVinci chips may include two separate power domains: "Always On" and "DSP".
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* Chips without a DSP generally have only one domain.
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*
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* The "Always On" power domain is always on when the chip is on, and is
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* powered by the VDD pins (on DM644X). The majority of DaVinci modules
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* lie within the "Always On" power domain.
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*
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* A separate domain called the "DSP" domain houses the C64x+ and other video
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* hardware such as VICP. In some chips, the "DSP" domain is not always on.
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* The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
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2008-07-11 19:10:13 +00:00
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*/
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/* Works on Always On power domain only (no PD argument) */
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2011-10-12 21:26:43 +00:00
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static void lpsc_transition(unsigned int id, unsigned int state)
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2008-07-11 19:10:13 +00:00
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{
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2009-11-12 16:07:22 +00:00
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dv_reg_p mdstat, mdctl, ptstat, ptcmd;
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struct davinci_psc_regs *psc_regs;
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2008-07-11 19:10:13 +00:00
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2009-11-12 16:07:22 +00:00
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if (id < DAVINCI_LPSC_PSC1_BASE) {
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if (id >= PSC_PSC0_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc0_regs;
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mdstat = &psc_regs->psc0.mdstat[id];
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mdctl = &psc_regs->psc0.mdctl[id];
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} else {
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id -= DAVINCI_LPSC_PSC1_BASE;
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if (id >= PSC_PSC1_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc1_regs;
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mdstat = &psc_regs->psc1.mdstat[id];
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mdctl = &psc_regs->psc1.mdctl[id];
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}
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ptstat = &psc_regs->ptstat;
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ptcmd = &psc_regs->ptcmd;
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2008-07-11 19:10:13 +00:00
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2009-11-12 16:07:22 +00:00
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while (readl(ptstat) & 0x01)
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2009-05-15 21:44:08 +00:00
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continue;
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2008-07-11 19:10:13 +00:00
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2011-10-12 21:26:43 +00:00
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if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
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return; /* Already in that state */
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2008-07-11 19:10:13 +00:00
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2011-10-12 21:26:43 +00:00
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writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
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2009-11-12 16:07:22 +00:00
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writel(0x01, ptcmd);
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2008-07-11 19:10:13 +00:00
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2009-11-12 16:07:22 +00:00
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while (readl(ptstat) & 0x01)
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2009-05-15 21:44:08 +00:00
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continue;
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2011-10-12 21:26:43 +00:00
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while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
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2009-05-15 21:44:08 +00:00
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continue;
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2008-07-11 19:10:13 +00:00
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}
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2011-10-12 21:26:43 +00:00
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void lpsc_on(unsigned int id)
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{
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lpsc_transition(id, 0x03);
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}
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void lpsc_syncreset(unsigned int id)
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{
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lpsc_transition(id, 0x01);
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}
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2012-08-09 10:45:20 +00:00
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void lpsc_disable(unsigned int id)
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{
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lpsc_transition(id, 0x0);
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}
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