2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2011-04-14 12:09:40 +00:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2011, Google Inc. All rights reserved.
|
2012-05-22 12:19:25 +00:00
|
|
|
* Portions Copyright 2011-2012 NVIDIA Corporation
|
2011-04-14 12:09:40 +00:00
|
|
|
*/
|
|
|
|
|
2012-09-19 22:50:56 +00:00
|
|
|
#ifndef _TEGRA20_GPIO_H_
|
|
|
|
#define _TEGRA20_GPIO_H_
|
2011-04-14 12:09:40 +00:00
|
|
|
|
|
|
|
/*
|
2011-06-17 06:27:28 +00:00
|
|
|
* The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
|
2011-04-14 12:09:40 +00:00
|
|
|
* each with 8 GPIOs.
|
|
|
|
*/
|
2011-06-17 06:27:28 +00:00
|
|
|
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
|
|
|
|
#define TEGRA_GPIO_BANKS 7 /* number of banks */
|
2012-09-19 22:50:56 +00:00
|
|
|
|
|
|
|
#include <asm/arch-tegra/gpio.h>
|
2011-04-14 12:09:40 +00:00
|
|
|
|
|
|
|
/* GPIO Controller registers for a single bank */
|
|
|
|
struct gpio_ctlr_bank {
|
|
|
|
uint gpio_config[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_dir_out[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_out[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_in[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_int_status[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_int_enable[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_int_level[TEGRA_GPIO_PORTS];
|
|
|
|
uint gpio_int_clear[TEGRA_GPIO_PORTS];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct gpio_ctlr {
|
|
|
|
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
|
|
|
|
};
|
|
|
|
|
2012-09-19 22:50:56 +00:00
|
|
|
#endif /* TEGRA20_GPIO_H_ */
|