mirror of
https://github.com/AsahiLinux/u-boot
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77 lines
1.5 KiB
Text
77 lines
1.5 KiB
Text
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Collabora Ltd.
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*
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* Based on dts[i] from Phytec barebox port:
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6ul-pcl063.dtsi"
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/ {
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model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
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compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
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"fsl,imx6ul";
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};
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&i2c1 {
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i2c_rtc: rtc@68 {
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compatible = "microcrystal,rv4162";
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reg = <0x68>;
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status = "okay";
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};
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
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MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
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MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
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MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
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>;
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};
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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>;
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};
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};
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