2010-04-20 15:20:33 +00:00
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2010-04-20 15:20:33 +00:00
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*/
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2008-03-24 14:40:32 +00:00
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#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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2010-04-20 15:20:33 +00:00
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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SRIO1,
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SRIO2,
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2010-07-13 03:51:29 +00:00
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SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5,
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2012-10-08 07:44:15 +00:00
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SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC10,
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2010-07-13 03:51:29 +00:00
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SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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2012-08-14 06:47:21 +00:00
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SGMII_FM2_DTSEC5,
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2012-10-08 07:44:15 +00:00
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SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC10,
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2010-04-20 15:20:33 +00:00
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC4,
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XAUI_FM1,
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XAUI_FM2,
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AURORA,
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2012-10-08 07:44:15 +00:00
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CPRI1,
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CPRI2,
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CPRI3,
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CPRI4,
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CPRI5,
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CPRI6,
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CPRI7,
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CPRI8,
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XAUI_FM1_MAC9,
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XAUI_FM1_MAC10,
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XAUI_FM2_MAC9,
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XAUI_FM2_MAC10,
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HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10,
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HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10,
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QSGMII_FM1_A, /* A indicates MACs 1-4 */
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QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
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QSGMII_FM2_A,
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QSGMII_FM2_B,
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2013-11-22 09:39:09 +00:00
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XFI_FM1_MAC1,
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XFI_FM1_MAC2,
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2012-10-08 07:44:15 +00:00
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XFI_FM1_MAC9,
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XFI_FM1_MAC10,
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XFI_FM2_MAC9,
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XFI_FM2_MAC10,
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INTERLAKEN,
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2014-01-24 12:21:50 +00:00
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QSGMII_SW1_A, /* Indicates ports on L2 Switch */
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2013-03-25 07:40:06 +00:00
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QSGMII_SW1_B,
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2014-10-23 09:20:57 +00:00
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SGMII_2500_FM1_DTSEC1,
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SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC3,
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SGMII_2500_FM1_DTSEC4,
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SGMII_2500_FM1_DTSEC5,
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SGMII_2500_FM1_DTSEC6,
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SGMII_2500_FM1_DTSEC9,
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SGMII_2500_FM1_DTSEC10,
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SGMII_2500_FM2_DTSEC1,
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SGMII_2500_FM2_DTSEC2,
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SGMII_2500_FM2_DTSEC3,
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SGMII_2500_FM2_DTSEC4,
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SGMII_2500_FM2_DTSEC5,
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SGMII_2500_FM2_DTSEC6,
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SGMII_2500_FM2_DTSEC9,
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SGMII_2500_FM2_DTSEC10,
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2012-10-08 07:44:15 +00:00
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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FSL_SRDS_3 = 2,
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FSL_SRDS_4 = 3,
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2010-04-20 15:20:33 +00:00
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};
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2008-03-24 14:40:32 +00:00
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2010-04-20 15:20:33 +00:00
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int is_serdes_configured(enum srds_prtcl device);
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2010-05-22 18:21:39 +00:00
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void fsl_serdes_init(void);
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2013-10-18 09:47:23 +00:00
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const char *serdes_clock_to_string(u32 clock);
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2008-03-24 14:40:32 +00:00
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2010-09-01 03:57:36 +00:00
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#ifdef CONFIG_FSL_CORENET
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2012-10-08 07:44:15 +00:00
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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2013-07-02 09:12:07 +00:00
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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2012-10-08 07:44:15 +00:00
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#else
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2010-09-01 03:57:36 +00:00
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int serdes_get_first_lane(enum srds_prtcl device);
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2012-10-08 07:44:15 +00:00
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#endif
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2010-09-01 03:57:38 +00:00
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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void serdes_reset_rx(enum srds_prtcl device);
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#endif
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2010-09-01 03:57:36 +00:00
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#endif
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2008-03-24 14:40:32 +00:00
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#endif /* __FSL_SERDES_H */
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