2018-05-06 21:58:06 +00:00
|
|
|
# SPDX-License-Identifier: GPL-2.0+
|
2007-11-24 20:17:55 +00:00
|
|
|
#
|
|
|
|
|
# (C) Copyright 2000-2007
|
|
|
|
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
|
|
|
|
2022-04-22 20:11:37 +00:00
|
|
|
obj-$(CONFIG_$(SPL_TPL_)MISC) += misc-uclass.o
|
misc: Add support for nvmem cells
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.
While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).
nvmem devices can specify "cells" in their device tree:
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00700000 0x100000>;
/* ... */
tsens_calibration: calib@404 {
reg = <0x404 0x10>;
};
};
which can then be referenced like:
tsens {
/* ... */
nvmem-cells = <&tsens_calibration>;
nvmem-cell-names = "calibration";
};
The tsens driver could then read the calibration value like:
struct nvmem_cell cal_cell;
u8 cal[16];
nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
nvmem_cell_read(&cal_cell, cal, sizeof(cal));
Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.
Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.
The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-05-05 17:11:39 +00:00
|
|
|
obj-$(CONFIG_$(SPL_TPL_)NVMEM) += nvmem.o
|
2018-11-18 15:14:27 +00:00
|
|
|
|
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
|
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
|
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
|
|
|
|
|
|
2016-01-22 02:43:52 +00:00
|
|
|
ifndef CONFIG_SPL_BUILD
|
2019-12-07 04:41:57 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += sandbox_adder.o
|
2013-10-17 08:34:57 +00:00
|
|
|
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
|
|
|
|
|
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
|
2019-12-07 04:41:57 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o
|
2019-09-25 14:56:42 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += swap_case.o
|
2016-02-23 05:55:43 +00:00
|
|
|
endif
|
2018-10-04 07:00:53 +00:00
|
|
|
|
2021-02-09 11:52:43 +00:00
|
|
|
ifdef CONFIG_$(SPL_)DM_I2C
|
2016-07-04 17:58:19 +00:00
|
|
|
ifndef CONFIG_SPL_BUILD
|
2014-12-10 15:55:51 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
|
2022-04-10 04:27:14 +00:00
|
|
|
obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o
|
2014-12-10 15:55:51 +00:00
|
|
|
endif
|
2016-07-04 17:58:19 +00:00
|
|
|
endif
|
2016-07-04 17:58:01 +00:00
|
|
|
ifdef CONFIG_SPL_OF_PLATDATA
|
|
|
|
|
ifdef CONFIG_SPL_BUILD
|
|
|
|
|
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
|
|
|
|
|
endif
|
|
|
|
|
endif
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
|
|
|
|
|
obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
|
|
|
|
|
obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
|
|
|
|
|
obj-$(CONFIG_DS4510) += ds4510.o
|
|
|
|
|
obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
|
2013-10-22 19:39:02 +00:00
|
|
|
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
|
2015-02-27 04:14:22 +00:00
|
|
|
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
|
2022-01-27 12:16:53 +00:00
|
|
|
obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
|
2022-03-08 00:24:04 +00:00
|
|
|
obj-$(CONFIG_GATEWORKS_SC) += gsc.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
|
|
|
|
|
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
|
2018-10-04 07:00:54 +00:00
|
|
|
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
|
2019-12-07 04:41:58 +00:00
|
|
|
obj-$(CONFIG_IRQ) += irq-uclass.o
|
2021-08-07 13:24:11 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
|
2018-10-04 07:00:55 +00:00
|
|
|
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_IMX8) += imx8/
|
2023-06-15 10:09:05 +00:00
|
|
|
obj-$(CONFIG_IMX_ELE) += imx_ele/
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_LED_STATUS) += status_led.o
|
|
|
|
|
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
|
|
|
|
|
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
|
arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.
The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.
The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.
I suggest using the following procedure for programming:
1. Override the fuses you wish to program
=> fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
=> fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
write-protect bit you will usually want to write it last anyway.
=> fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
=> fuse read 0 2 4
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-22 18:34:18 +00:00
|
|
|
obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
|
2021-09-25 16:49:28 +00:00
|
|
|
obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
|
2022-06-07 08:33:54 +00:00
|
|
|
obj-$(CONFIG_NPCM_OTP) += npcm_otp.o
|
2022-06-24 08:24:37 +00:00
|
|
|
obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
|
2019-12-07 04:41:55 +00:00
|
|
|
obj-$(CONFIG_P2SB) += p2sb-uclass.o
|
2015-03-12 10:22:46 +00:00
|
|
|
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
|
2023-04-21 17:50:33 +00:00
|
|
|
obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
|
2021-03-19 07:21:40 +00:00
|
|
|
ifdef CONFIG_QFW
|
|
|
|
|
obj-y += qfw.o
|
2023-12-19 15:04:01 +00:00
|
|
|
obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o
|
2021-03-19 07:21:40 +00:00
|
|
|
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
|
2021-03-19 07:21:42 +00:00
|
|
|
obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o
|
2021-03-19 07:21:41 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
|
2021-03-19 07:21:40 +00:00
|
|
|
endif
|
2017-05-05 17:21:38 +00:00
|
|
|
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
|
2019-09-25 15:57:49 +00:00
|
|
|
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
|
2023-08-21 22:30:28 +00:00
|
|
|
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
|
2020-05-29 06:03:21 +00:00
|
|
|
obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
|
|
|
|
|
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
|
2018-05-17 13:24:06 +00:00
|
|
|
obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
|
2017-12-15 21:01:00 +00:00
|
|
|
obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
|
|
|
|
|
obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
|
2020-12-23 15:11:18 +00:00
|
|
|
obj-$(CONFIG_TEST_DRV) += test_drv.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
|
2018-09-28 12:43:31 +00:00
|
|
|
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
|
2018-10-04 07:00:53 +00:00
|
|
|
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
|
2018-12-16 22:25:19 +00:00
|
|
|
obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
|
2019-10-09 09:23:39 +00:00
|
|
|
obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
|
2019-10-24 09:30:46 +00:00
|
|
|
obj-$(CONFIG_K3_AVS0) += k3_avs.o
|
2020-02-14 09:18:15 +00:00
|
|
|
obj-$(CONFIG_ESM_K3) += k3_esm.o
|
2020-02-14 09:18:16 +00:00
|
|
|
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
|
2022-02-25 12:36:24 +00:00
|
|
|
obj-$(CONFIG_SL28CPLD) += sl28cpld.o
|
