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u-boot/arch/mips/include/asm/cache.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Shinya Kuribayashi <skuribay@pobox.com>
2011-10-17 23:46:11 +00:00
/*
* Copyright (c) 2011 The Chromium OS Authors.
*/
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-26 15:47:59 +00:00
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
MIPS: Split I & D cache line size config Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-27 13:28:05 +00:00
mips: Let cache.h be included from assembly source Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-25 22:32:22 +00:00
#ifndef __ASSEMBLY__
MIPS: Probe cache line sizes once during boot Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:48 +00:00
/**
* mips_cache_probe() - Probe the properties of the caches
*
* Call this to probe the properties such as line sizes of the caches
* present in the system, if any. This must be done before cache maintenance
* functions such as flush_cache may be called.
*/
void mips_cache_probe(void);
mips: Let cache.h be included from assembly source Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-25 22:32:22 +00:00
#endif
MIPS: Probe cache line sizes once during boot Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:48 +00:00
mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Shinya Kuribayashi <skuribay@pobox.com>
2011-10-17 23:46:11 +00:00
#endif /* __MIPS_CACHE_H__ */
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