2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-02-09 12:36:58 +00:00
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/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*/
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/*
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* This file should be included in board config header file.
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*
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* It supports common definitions for Kirkwood platform
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*/
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#ifndef _KW_CONFIG_H
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#define _KW_CONFIG_H
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#if defined (CONFIG_KW88F6281)
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#include <asm/arch/kw88f6281.h>
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#elif defined (CONFIG_KW88F6192)
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#include <asm/arch/kw88f6192.h>
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#else
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#error "SOC Name not defined"
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#endif /* CONFIG_KW88F6281 */
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2014-10-22 10:13:06 +00:00
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#include <asm/arch/soc.h>
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2011-02-09 12:36:58 +00:00
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2022-12-04 15:04:09 +00:00
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#define CFG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
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2011-02-09 12:36:58 +00:00
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#define MV_UART_CONSOLE_BASE KW_UART0_BASE
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#define MV_SATA_BASE KW_SATA_BASE
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#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
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#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
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/*
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* NAND configuration
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*/
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#ifdef CONFIG_CMD_NAND
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
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2011-02-09 12:36:58 +00:00
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#define NAND_ALLOW_ERASE_ALL 1
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#endif
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/*
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* IDE Support on SATA ports
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*/
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2017-05-17 09:25:30 +00:00
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#ifdef CONFIG_IDE
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2011-02-09 12:36:58 +00:00
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#define __io
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/* Data, registers and alternate blocks are at the same offset */
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/* Each 8-bit ATA register is aligned to a 4-bytes address */
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2017-05-17 09:25:30 +00:00
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/* CONFIG_IDE requires some #defines for ATA registers */
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2011-02-09 12:36:58 +00:00
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/* ATA registers base is at SATA controller base */
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2017-05-17 09:25:30 +00:00
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#endif /* CONFIG_IDE */
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2011-02-09 12:36:58 +00:00
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2015-10-22 10:36:31 +00:00
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/* Use common timer */
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2022-08-17 19:37:50 +00:00
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#ifndef CONFIG_TIMER
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
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#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK
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2022-08-17 19:37:50 +00:00
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#endif
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2015-10-22 10:36:31 +00:00
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2011-02-09 12:36:58 +00:00
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#endif /* _KW_CONFIG_H */
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