2007-03-26 22:32:16 +00:00
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/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
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*/
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2007-03-25 23:39:07 +00:00
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 100000000
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/* Interrupt controller is opb_intc_0 */
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#define XILINX_INTC_BASEADDR 0x41200000
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#define XILINX_INTC_NUM_INTR_INPUTS 11
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/* Timer pheriphery is opb_timer_1 */
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#define XILINX_TIMER_BASEADDR 0x41c00000
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#define XILINX_TIMER_IRQ 1
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/* Uart pheriphery is RS232_Uart_1 */
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#define XILINX_UART_BASEADDR 0x40600000
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#define XILINX_UART_BAUDRATE 115200
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/* GPIO is LEDs_4Bit*/
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#define XILINX_GPIO_BASEADDR 0x40000000
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/* FLASH doesn't exist none */
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/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
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#define XILINX_RAM_START 0x30000000
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#define XILINX_RAM_SIZE 0x10000000
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/* Sysace Controller is SysACE_CompactFlash */
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#define XILINX_SYSACE_BASEADDR 0x41800000
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#define XILINX_SYSACE_HIGHADDR 0x4180ffff
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#define XILINX_SYSACE_MEM_WIDTH 16
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/* Ethernet controller is Ethernet_MAC */
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#define XPAR_XEMAC_NUM_INSTANCES 1
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#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
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#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
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#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
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#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
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#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
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#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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