Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-16 00:03:24 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/cpu/armv7/psci.S

323 lines
8.3 KiB
ArmAsm
Raw Normal View History

ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
/*
* Copyright (C) 2013,2014 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <linux/linkage.h>
ARM: Put target PC for PSCI CPU_ON on per-CPU stack Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:30 +00:00
#include <asm/macro.h>
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl _psci_vectors
_psci_vectors:
b default_psci_vector @ reset
b default_psci_vector @ undef
b _smc_psci @ smc
b default_psci_vector @ pabort
b default_psci_vector @ dabort
b default_psci_vector @ hyp
b default_psci_vector @ irq
b psci_fiq_enter @ fiq
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_fiq_enter)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
movs pc, lr
ENDPROC(psci_fiq_enter)
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(default_psci_vector)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
movs pc, lr
ENDPROC(default_psci_vector)
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_version)
WEAK(psci_cpu_suspend)
WEAK(psci_cpu_off)
WEAK(psci_cpu_on)
WEAK(psci_affinity_info)
WEAK(psci_migrate)
WEAK(psci_migrate_info_type)
WEAK(psci_migrate_info_up_cpu)
WEAK(psci_system_off)
WEAK(psci_system_reset)
WEAK(psci_features)
WEAK(psci_cpu_freeze)
WEAK(psci_cpu_default_suspend)
WEAK(psci_node_hw_state)
WEAK(psci_system_suspend)
WEAK(psci_set_suspend_mode)
WEAK(psi_stat_residency)
WEAK(psci_stat_count)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ARMv7: PSCI: add PSCI v1.0 functions skeleton This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 10:09:36 +00:00
ENDPROC(psci_stat_count)
ENDPROC(psi_stat_residency)
ENDPROC(psci_set_suspend_mode)
ENDPROC(psci_system_suspend)
ENDPROC(psci_node_hw_state)
ENDPROC(psci_cpu_default_suspend)
ENDPROC(psci_cpu_freeze)
ENDPROC(psci_features)
ENDPROC(psci_system_reset)
ENDPROC(psci_system_off)
ENDPROC(psci_migrate_info_up_cpu)
ENDPROC(psci_migrate_info_type)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
ENDPROC(psci_migrate)
ARMv7: PSCI: add PSCI v1.0 functions skeleton This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 10:09:36 +00:00
ENDPROC(psci_affinity_info)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
ARMv7: PSCI: add PSCI v1.0 functions skeleton This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 10:09:36 +00:00
ENDPROC(psci_version)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
ARMv7: PSCI: add PSCI v1.0 functions skeleton This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 10:09:36 +00:00
.word ARM_PSCI_0_2_FN_PSCI_VERSION
.word psci_version
.word ARM_PSCI_0_2_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_0_2_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_0_2_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_0_2_FN_AFFINITY_INFO
.word psci_affinity_info
.word ARM_PSCI_0_2_FN_MIGRATE
.word psci_migrate
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
.word psci_migrate_info_type
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
.word psci_migrate_info_up_cpu
.word ARM_PSCI_0_2_FN_SYSTEM_OFF
.word psci_system_off
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word psci_system_reset
.word ARM_PSCI_1_0_FN_PSCI_FEATURES
.word psci_features
.word ARM_PSCI_1_0_FN_CPU_FREEZE
.word psci_cpu_freeze
.word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
.word psci_cpu_default_suspend
.word ARM_PSCI_1_0_FN_NODE_HW_STATE
.word psci_node_hw_state
.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
.word psci_system_suspend
.word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
.word psci_set_suspend_mode
.word ARM_PSCI_1_0_FN_STAT_RESIDENCY
.word psi_stat_residency
.word ARM_PSCI_1_0_FN_STAT_COUNT
.word psci_stat_count
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
.word 0
.word 0
_smc_psci:
push {r4-r7,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
bic r4, r7, #1
mcr p15, 0, r4, c1, c1, 0
isb
adr r4, _psci_table
1: ldr r5, [r4] @ Load PSCI function ID
ldr r6, [r4, #4] @ Load target PC
cmp r5, #0 @ If reach the end, bail out
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
beq 2f
cmp r0, r5 @ If not matching, try next entry
addne r4, r4, #8
bne 1b
blx r6 @ Execute PSCI function
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
pop {r4-r7, lr}
movs pc, lr @ Return to the kernel
ARM: Factor out common psci_get_cpu_id Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:26 +00:00
@ Requires dense and single-cluster CPU ID space
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_get_cpu_id)
ARM: Factor out common psci_get_cpu_id Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:26 +00:00
mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
and r0, r0, #0xff /* return CPU ID in cluster */
bx lr
ENDPROC(psci_get_cpu_id)
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
/* Imported from Linux kernel */
armv7: psci: make v7_flush_dcache_all public for all psci code The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-19 09:20:30 +00:00
ENTRY(psci_v7_flush_dcache_all)
ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-07 02:54:25 +00:00
stmfd sp!, {r4-r5, r7, r9-r11, lr}
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
mov r3, r3, lsr #23 @ left align loc bit field
beq finished @ if loc is 0, then no need to clean
mov r10, #0 @ start clean at cache level 0
flush_levels:
add r2, r10, r10, lsr #1 @ work out 3x current cache level
mov r1, r0, lsr r2 @ extract cache type bits from clidr
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
mrs r9, cpsr @ make cssr&csidr read atomic
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
msr cpsr_c, r9
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
clz r5, r4 @ find bit position of way size increment
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 @ extract max number of the index size
loop1:
mov r9, r7 @ create working copy of max index
loop2:
orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
orr r11, r11, r9, lsl r2 @ factor index number into r11
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
subs r9, r9, #1 @ decrement the index
bge loop2
subs r4, r4, #1 @ decrement the way
bge loop1
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
bgt flush_levels
finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb st
isb
ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-07 02:54:25 +00:00
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
bx lr
armv7: psci: make v7_flush_dcache_all public for all psci code The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-19 09:20:30 +00:00
ENDPROC(psci_v7_flush_dcache_all)
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_disable_smp)
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
bic r0, r0, #(1 << 6) @ Clear SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
dsb
bx lr
ENDPROC(psci_disable_smp)
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_enable_smp)
ARM: Factor out reusable psci_cpu_entry _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:28 +00:00
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
bx lr
ENDPROC(psci_enable_smp)
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
ENTRY(psci_cpu_off_common)
push {lr}
armv7: psci: cpu_off: flush D-Cache before disable D-Cache Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
2016-11-22 11:41:09 +00:00
bl psci_v7_flush_dcache_all
clrex @ Why???
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
mrc p15, 0, r0, c1, c0, 0 @ SCTLR
bic r0, r0, #(1 << 2) @ Clear C bit
mcr p15, 0, r0, c1, c0, 0 @ SCTLR
isb
dsb
armv7: psci: make v7_flush_dcache_all public for all psci code The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-19 09:20:30 +00:00
bl psci_v7_flush_dcache_all
ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:27 +00:00
clrex @ Why???
bl psci_disable_smp
pop {lr}
bx lr
ENDPROC(psci_cpu_off_common)
ARM: PSCI: Allocate PSCI stack in secure stack section Now that we have a secure stack section that guarantees usable memory, allocate the PSCI stacks in that section. Also add a diagram detailing how the stacks are placed in memory. Reserved space for the target PC remains unchanged. This should be moved to global variables within a secure data section in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:37 +00:00
@ The stacks are allocated in reverse order, i.e.
@ the stack for CPU0 has the highest memory address.
@
@ -------------------- __secure_stack_end
@ | CPU0 target PC |
@ |------------------|
@ | |
@ | CPU0 stack |
@ | |
@ |------------------| __secure_stack_end - 1KB
@ | . |
@ | . |
@ | . |
@ | . |
@ -------------------- __secure_stack_start
@
@ This expects CPU ID in r0 and returns stack top in r0
ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address. Make psci_get_cpu_stack_top a local function, as it should only be used in armv7/psci.S and only by psci_stack_setup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:45 +00:00
LENTRY(psci_get_cpu_stack_top)
ARM: PSCI: Allocate PSCI stack in secure stack section Now that we have a secure stack section that guarantees usable memory, allocate the PSCI stacks in that section. Also add a diagram detailing how the stacks are placed in memory. Reserved space for the target PC remains unchanged. This should be moved to global variables within a secure data section in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:37 +00:00
@ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
ldr r3, =__secure_stack_end
sub r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
sub r0, r0, #4 @ Save space for target PC
ARM: Factor out reusable psci_get_cpu_stack_top This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:29 +00:00
bx lr
ENDPROC(psci_get_cpu_stack_top)
ARM: PSCI: Split out common stack setup code from psci_arch_init Every platform has the same stack setup code in assembly as part of psci_arch_init. Move this out into a common separate function, psci_stack_setup, for all platforms. This will allow us to move the remaining parts of psci_arch_init into C code, or drop it entirely. Also provide a stub no-op psci_arch_init for platforms that don't need their own specific setup code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:31 +00:00
@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
@ this function.
ENTRY(psci_stack_setup)
mov r6, lr
mov r7, r0
bl psci_get_cpu_id @ CPU ID => r0
bl psci_get_cpu_stack_top @ stack top => r0
mov sp, r0
mov r0, r7
bx r6
ENDPROC(psci_stack_setup)
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_arch_init)
ARM: PSCI: Split out common stack setup code from psci_arch_init Every platform has the same stack setup code in assembly as part of psci_arch_init. Move this out into a common separate function, psci_stack_setup, for all platforms. This will allow us to move the remaining parts of psci_arch_init into C code, or drop it entirely. Also provide a stub no-op psci_arch_init for platforms that don't need their own specific setup code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:31 +00:00
mov pc, lr
ENDPROC(psci_arch_init)
arm: Use the WEAK assembly entry point consistently It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-11-22 17:31:56 +00:00
WEAK(psci_arch_cpu_entry)
arm: psci: add a weak function psci_arch_cpu_entry The added function psci_arch_cpu_entry() is called during psci_cpu_entry() and can be used by arch to handle PSCI state transition from ON_PENDING to ON. The default weak function is empty: not behavior change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-04-16 08:13:23 +00:00
mov pc, lr
ENDPROC(psci_arch_cpu_entry)
ARM: Factor out reusable psci_cpu_entry _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:28 +00:00
ENTRY(psci_cpu_entry)
bl psci_enable_smp
bl _nonsec_init
ARM: PSCI: initialize stack pointer on secondary CPUs A proper stack is required to safely use C code in psci_arch_cpu_entry. Fixes: 486daaa618e1 ("arm: psci: add a weak function psci_arch_cpu_entry") Cc: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Patrick DELAUNAY <Patrick.delaunay@st.com> Tested-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
2018-06-24 19:09:54 +00:00
bl psci_stack_setup
arm: psci: add a weak function psci_arch_cpu_entry The added function psci_arch_cpu_entry() is called during psci_cpu_entry() and can be used by arch to handle PSCI state transition from ON_PENDING to ON. The default weak function is empty: not behavior change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-04-16 08:13:23 +00:00
bl psci_arch_cpu_entry
ARM: Put target PC for PSCI CPU_ON on per-CPU stack Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:30 +00:00
bl psci_get_cpu_id @ CPU ID => r0
arm: psci: save context id for cpu_on PSCI command Save and use the 3rd parameter of PSCI CPU_ON request: context_id. The context_id parameter is only meaningful to the caller. U-Boot PSCI preserves a copy of the value passed in this parameter. Following wakeup from a powerdown state, U-BOOT PSCI places this value in R0 when it first enters the OS. NB: this context id is not (yet?) used by Linux but it is mandatory to be PSCI compliant. update armv7 psci functions: - psci_save_target_pc(): keep for backward compatibility with current platform (only save PC and force context id to 0) => should be removed when all platform migrate to the new API - psci_save(): new API to use by ARMv7 platform with PSCI, save pc (= entry_point_address) and context_id Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-16 08:13:22 +00:00
bl psci_get_context_id @ context id => r0
psci: fix use of clobbered registers in asm The functions `psci_get_context_id` and `psci_get_target_pc` are written in C, so the C compiler may clobber registers r0-r3. Do not use these registers to save data across calls. Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-05-28 00:09:42 +00:00
push {r0} @ save context id
bl psci_get_cpu_id @ CPU ID => r0
ARM: PSCI: Switch to per-CPU target PC storage in secure data section Now that we have a secure data section and space to store per-CPU target PC address, switch to it instead of storing the target PC on the stack. Also save clobbered r4-r7 registers on the stack and restore them on return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 04:38:44 +00:00
bl psci_get_target_pc @ target PC => r0
psci: fix use of clobbered registers in asm The functions `psci_get_context_id` and `psci_get_target_pc` are written in C, so the C compiler may clobber registers r0-r3. Do not use these registers to save data across calls. Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-05-28 00:09:42 +00:00
pop {r1} @ context id => r1
ARM: Factor out reusable psci_cpu_entry _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-04-21 05:18:28 +00:00
b _do_nonsec_entry
ENDPROC(psci_cpu_entry)
ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-12 13:24:04 +00:00
.popsection
Reference in a new issue Copy permalink