Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-12 06:12:58 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi

659 lines
18 KiB
Text
Raw Normal View History

arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
sms: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
mboxes = <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
ranges = <0x00 0x00 0x41c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
reg = <0x00 0x4301c000 0x00 0x034>;
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x02C>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx2: pinctrl@4301c068 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx3: pinctrl@4301c190 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c190 0x00 0x004>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04200 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04280 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
ti,interrupt-ranges = <16 960 16>;
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
mcu_timer0: timer@40400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer1: timer@40410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 83 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 83 1>;
assigned-clock-parents = <&k3_clks 83 2>;
power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer2: timer@40420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 84 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 84 1>;
assigned-clock-parents = <&k3_clks 84 2>;
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer3: timer@40430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 85 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 85 1>;
assigned-clock-parents = <&k3_clks 85 2>;
power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer4: timer@40440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40440000 0x00 0x400>;
interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 86 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 86 1>;
assigned-clock-parents = <&k3_clks 86 2>;
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer5: timer@40450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40450000 0x00 0x400>;
interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 87 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 87 1>;
assigned-clock-parents = <&k3_clks 87 2>;
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer6: timer@40460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40460000 0x00 0x400>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 88 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 88 1>;
assigned-clock-parents = <&k3_clks 88 2>;
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer7: timer@40470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40470000 0x00 0x400>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 89 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 89 1>;
assigned-clock-parents = <&k3_clks 89 2>;
power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer8: timer@40480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40480000 0x00 0x400>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 90 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 90 1>;
assigned-clock-parents = <&k3_clks 90 2>;
power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer9: timer@40490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40490000 0x00 0x400>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 91 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x200>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
interrupt-parent = <&wkup_gpio_intr>;
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 115 0>;
clock-names = "gpio";
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
wkup_gpio1: gpio@42100000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
interrupt-parent = <&wkup_gpio_intr>;
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 116 0>;
clock-names = "gpio";
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
wkup_i2c0: i2c@42120000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x42120000 0x00 0x100>;
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b00000 0x00 0x100>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_i2c1: i2c@40b10000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b10000 0x00 0x100>;
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_mcan0: can@40528000 {
compatible = "bosch,m_can";
reg = <0x00 0x40528000 0x00 0x200>,
<0x00 0x40500000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
mcu_mcan1: can@40568000 {
compatible = "bosch,m_can";
reg = <0x00 0x40568000 0x00 0x200>,
<0x00 0x40540000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
status = "disabled";
};
mcu_spi0: spi@40300000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040300000 0x00 0x400>;
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 347 0>;
status = "disabled";
};
mcu_spi1: spi@40310000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040310000 0x00 0x400>;
interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 348 0>;
status = "disabled";
};
mcu_spi2: spi@40320000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040320000 0x00 0x400>;
interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 349 0>;
status = "disabled";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
mcu_navss: bus@28380000 {
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <267>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <272>;
msi-parent = <&main_udmass_inta>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <273>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>; /* TX_HCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x2a480000 0x00 0x80000>,
<0x00 0x2a380000 0x00 0x80000>,
<0x00 0x2a400000 0x00 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x46000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
dma-coherent;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
dmas = <&mcu_udmap 0xf000>,
<&mcu_udmap 0xf001>,
<&mcu_udmap 0xf002>,
<&mcu_udmap 0xf003>,
<&mcu_udmap 0xf004>,
<&mcu_udmap 0xf005>,
<&mcu_udmap 0xf006>,
<&mcu_udmap 0xf007>,
<&mcu_udmap 0x7000>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
phys = <&phy_gmii_sel 1>;
};
};
davinci_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1 The following commit syncs the device tree from Linux tag v6.6-rc1 to U-boot and fixes the following to be compatible with the future syncs - - Include k3-j721s2-common-proc-board.dts file Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and include k3-j721s2-common-proc-board.dts for Linux fixes to propagate to U-boot. - Fixing the mcu_timer0 Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi - Fixing secure proxy nodes Linux DT now have these nodes defined so remove them and rename to use the Linux DT ones. - Remove cpsw node The compatible is now fixed and the node is not required in -u-boot specifically - Remove aliases and chosen node Use these from Linux and don't override when not required. - Remove /delete-property/ from sdhci nodes We have the necessary clock and dev data so remove these. - Remove dummy_clocks and fs_loader0 These weren't being used anywhere so remove it. - Remove mcu_ringacc override All these have been put in a single commit to not break the bisectability. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-06 04:45:58 +00:00
tscadc0: tscadc@40200000 {
compatible = "ti,am3359-tscadc";
reg = <0x00 0x40200000 0x00 0x1000>;
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
tscadc1: tscadc@40210000 {
compatible = "ti,am3359-tscadc";
reg = <0x00 0x40210000 0x00 0x1000>;
interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 1 0>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47040000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 109 5>;
assigned-clocks = <&k3_clks 109 5>;
assigned-clock-parents = <&k3_clks 109 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* Needs pinmux */
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47050000 0x00 0x100>,
<0x07 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 110 5>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* Needs pinmux */
};
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x0 0x350>,
<0x00 0x42050000 0x0 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
arm: dts: Add initial support for J721S2 SoC The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-01-25 15:26:40 +00:00
};
Reference in a new issue Copy permalink