2013-01-18 16:14:24 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
|
|
|
* Jason Liu <r64343@freescale.com>
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2013-01-18 16:14:24 +00:00
|
|
|
*
|
2013-04-30 11:15:33 +00:00
|
|
|
* Refer doc/README.imximage for more details about how-to configure
|
2013-01-18 16:14:24 +00:00
|
|
|
* and create imximage boot image
|
|
|
|
*
|
|
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* image version */
|
2011-12-29 06:34:19 +00:00
|
|
|
IMAGE_VERSION 2
|
|
|
|
|
2013-01-18 16:14:24 +00:00
|
|
|
/*
|
|
|
|
* Boot Device : one of
|
|
|
|
* spi, sd (the board has no nand neither onenand)
|
|
|
|
*/
|
2011-12-29 06:34:19 +00:00
|
|
|
BOOT_FROM sd
|
|
|
|
|
2013-01-18 16:14:24 +00:00
|
|
|
/*
|
|
|
|
* Device Configuration Data (DCD)
|
|
|
|
*
|
|
|
|
* Each entry must have the format:
|
|
|
|
* Addr-type Address Value
|
|
|
|
*
|
|
|
|
* where:
|
|
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
|
|
* Address absolute address of the register
|
|
|
|
* value value to be stored in the register
|
|
|
|
*/
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x020e05a8 0x00000030
|
|
|
|
DATA 4 0x020e05b0 0x00000030
|
|
|
|
DATA 4 0x020e0524 0x00000030
|
|
|
|
DATA 4 0x020e051c 0x00000030
|
|
|
|
|
|
|
|
DATA 4 0x020e0518 0x00000030
|
|
|
|
DATA 4 0x020e050c 0x00000030
|
|
|
|
DATA 4 0x020e05b8 0x00000030
|
|
|
|
DATA 4 0x020e05c0 0x00000030
|
|
|
|
|
|
|
|
DATA 4 0x020e05ac 0x00020030
|
|
|
|
DATA 4 0x020e05b4 0x00020030
|
|
|
|
DATA 4 0x020e0528 0x00020030
|
|
|
|
DATA 4 0x020e0520 0x00020030
|
|
|
|
|
|
|
|
DATA 4 0x020e0514 0x00020030
|
|
|
|
DATA 4 0x020e0510 0x00020030
|
|
|
|
DATA 4 0x020e05bc 0x00020030
|
|
|
|
DATA 4 0x020e05c4 0x00020030
|
|
|
|
|
|
|
|
DATA 4 0x020e056c 0x00020030
|
|
|
|
DATA 4 0x020e0578 0x00020030
|
|
|
|
DATA 4 0x020e0588 0x00020030
|
|
|
|
DATA 4 0x020e0594 0x00020030
|
|
|
|
|
|
|
|
DATA 4 0x020e057c 0x00020030
|
|
|
|
DATA 4 0x020e0590 0x00003000
|
|
|
|
DATA 4 0x020e0598 0x00003000
|
|
|
|
DATA 4 0x020e058c 0x00000000
|
|
|
|
|
|
|
|
DATA 4 0x020e059c 0x00003030
|
|
|
|
DATA 4 0x020e05a0 0x00003030
|
|
|
|
DATA 4 0x020e0784 0x00000030
|
|
|
|
DATA 4 0x020e0788 0x00000030
|
|
|
|
|
|
|
|
DATA 4 0x020e0794 0x00000030
|
|
|
|
DATA 4 0x020e079c 0x00000030
|
|
|
|
DATA 4 0x020e07a0 0x00000030
|
|
|
|
DATA 4 0x020e07a4 0x00000030
|
|
|
|
|
|
|
|
DATA 4 0x020e07a8 0x00000030
|
|
|
|
DATA 4 0x020e0748 0x00000030
|
|
|
|
DATA 4 0x020e074c 0x00000030
|
|
|
|
DATA 4 0x020e0750 0x00020000
|
|
|
|
|
|
|
|
DATA 4 0x020e0758 0x00000000
|
|
|
|
DATA 4 0x020e0774 0x00020000
|
|
|
|
DATA 4 0x020e078c 0x00000030
|
|
|
|
DATA 4 0x020e0798 0x000C0000
|
|
|
|
|
|
|
|
DATA 4 0x021b081c 0x33333333
|
|
|
|
DATA 4 0x021b0820 0x33333333
|
|
|
|
DATA 4 0x021b0824 0x33333333
|
|
|
|
DATA 4 0x021b0828 0x33333333
|
|
|
|
|
|
|
|
DATA 4 0x021b481c 0x33333333
|
|
|
|
DATA 4 0x021b4820 0x33333333
|
|
|
|
DATA 4 0x021b4824 0x33333333
|
|
|
|
DATA 4 0x021b4828 0x33333333
|
|
|
|
|
|
|
|
DATA 4 0x021b0018 0x00081740
|
|
|
|
|
|
|
|
DATA 4 0x021b001c 0x00008000
|
imx: mx6q DDR3 init: Benefit from available CL = 7
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-01-30 11:19:18 +00:00
|
|
|
DATA 4 0x021b000c 0x555A7974
|
|
|
|
DATA 4 0x021b0010 0xDB538F64
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x021b0014 0x01FF00DB
|
|
|
|
DATA 4 0x021b002c 0x000026D2
|
|
|
|
|
2013-01-30 11:19:16 +00:00
|
|
|
DATA 4 0x021b0030 0x005A1023
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x021b0008 0x09444040
|
|
|
|
DATA 4 0x021b0004 0x00025576
|
|
|
|
DATA 4 0x021b0040 0x00000027
|
|
|
|
DATA 4 0x021b0000 0x831A0000
|
|
|
|
|
|
|
|
DATA 4 0x021b001c 0x04088032
|
|
|
|
DATA 4 0x021b001c 0x0408803A
|
|
|
|
DATA 4 0x021b001c 0x00008033
|
|
|
|
DATA 4 0x021b001c 0x0000803B
|
|
|
|
DATA 4 0x021b001c 0x00428031
|
|
|
|
DATA 4 0x021b001c 0x00428039
|
imx: mx6q DDR3 init: Benefit from available CL = 7
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-01-30 11:19:18 +00:00
|
|
|
DATA 4 0x021b001c 0x19308030
|
|
|
|
DATA 4 0x021b001c 0x19308038
|
2011-12-29 06:34:19 +00:00
|
|
|
|
|
|
|
DATA 4 0x021b001c 0x04008040
|
|
|
|
DATA 4 0x021b001c 0x04008048
|
|
|
|
DATA 4 0x021b0800 0xA1380003
|
|
|
|
DATA 4 0x021b4800 0xA1380003
|
|
|
|
DATA 4 0x021b0020 0x00005800
|
|
|
|
DATA 4 0x021b0818 0x00022227
|
|
|
|
DATA 4 0x021b4818 0x00022227
|
|
|
|
|
|
|
|
DATA 4 0x021b083c 0x434B0350
|
|
|
|
DATA 4 0x021b0840 0x034C0359
|
|
|
|
DATA 4 0x021b483c 0x434B0350
|
|
|
|
DATA 4 0x021b4840 0x03650348
|
|
|
|
DATA 4 0x021b0848 0x4436383B
|
|
|
|
DATA 4 0x021b4848 0x39393341
|
|
|
|
DATA 4 0x021b0850 0x35373933
|
|
|
|
DATA 4 0x021b4850 0x48254A36
|
|
|
|
|
|
|
|
DATA 4 0x021b080c 0x001F001F
|
|
|
|
DATA 4 0x021b0810 0x001F001F
|
|
|
|
|
|
|
|
DATA 4 0x021b480c 0x00440044
|
|
|
|
DATA 4 0x021b4810 0x00440044
|
|
|
|
|
|
|
|
DATA 4 0x021b08b8 0x00000800
|
|
|
|
DATA 4 0x021b48b8 0x00000800
|
|
|
|
|
|
|
|
DATA 4 0x021b001c 0x00000000
|
|
|
|
DATA 4 0x021b0404 0x00011006
|
|
|
|
|
2013-01-18 16:14:24 +00:00
|
|
|
/* set the default clock gate to save power */
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x020c4068 0x00C03F3F
|
2012-01-31 07:52:05 +00:00
|
|
|
DATA 4 0x020c406c 0x0030FC03
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x020c4070 0x0FFFC000
|
|
|
|
DATA 4 0x020c4074 0x3FF00000
|
|
|
|
DATA 4 0x020c4078 0x00FFF300
|
|
|
|
DATA 4 0x020c407c 0x0F0000C3
|
|
|
|
DATA 4 0x020c4080 0x000003FF
|
|
|
|
|
2013-01-18 16:14:24 +00:00
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
2012-06-12 04:50:33 +00:00
|
|
|
DATA 4 0x020e0010 0xF00000CF
|
2013-01-18 16:14:24 +00:00
|
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
2011-12-29 06:34:19 +00:00
|
|
|
DATA 4 0x020e0018 0x007F007F
|
|
|
|
DATA 4 0x020e001c 0x007F007F
|
2013-04-17 08:33:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup CCM_CCOSR register as follows:
|
|
|
|
*
|
|
|
|
* cko1_en = 1 --> CKO1 enabled
|
|
|
|
* cko1_div = 111 --> divide by 8
|
|
|
|
* cko1_sel = 1011 --> ahb_clk_root
|
|
|
|
*
|
|
|
|
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
|
|
|
|
*/
|
|
|
|
DATA 4 0x020c4060 0x000000fb
|