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u-boot/drivers/pinctrl/nxp/pinctrl-imx.h

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pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
/*
* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DRIVERS_PINCTRL_IMX_H
#define __DRIVERS_PINCTRL_IMX_H
/**
* @base: the address to the controller in virtual memory
* @input_sel_base: the address of the select input in virtual memory.
* @flags: flags specific for each soc
pinctrl: Add i.MX7ULP pinctrl driver Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-02-22 08:21:49 +00:00
* @mux_mask: Used when SHARE_MUX_CONF_REG flag is added
pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
*/
struct imx_pinctrl_soc_info {
void __iomem *base;
void __iomem *input_sel_base;
unsigned int flags;
pinctrl: Add i.MX7ULP pinctrl driver Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-02-22 08:21:49 +00:00
unsigned int mux_mask;
pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
};
/**
* @dev: a pointer back to containing device
* @info: the soc info
*/
struct imx_pinctrl_priv {
struct udevice *dev;
struct imx_pinctrl_soc_info *info;
};
extern const struct pinctrl_ops imx_pinctrl_ops;
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
#define IMX_PAD_SION 0x40000000 /* set SION */
/*
* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
pinctrl: Add i.MX7ULP pinctrl driver Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-02-22 08:21:49 +00:00
#define CONFIG_IBE_OBE 0x4
pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
#define IOMUXC_CONFIG_SION (0x1 << 4)
int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
int imx_pinctrl_remove(struct udevice *dev);
#endif /* __DRIVERS_PINCTRL_IMX_H */
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