2021-06-02 07:58:25 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_RK3568_COMMON_H
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#define __CONFIG_RK3568_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_IRAM_BASE 0xfdcc0000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
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2021-10-26 02:42:19 +00:00
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#define CONFIG_SPL_STACK 0x00400000
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#define CONFIG_SPL_BSS_START_ADDR 0x4000000
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2021-06-02 07:58:25 +00:00
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xf0000000
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00c00000\0" \
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"pxefile_addr_r=0x00e00000\0" \
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"fdt_addr_r=0x0a100000\0" \
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"kernel_addr_r=0x02080000\0" \
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"ramdisk_addr_r=0x0a200000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#endif
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