2019-04-10 08:43:34 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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2021-06-03 02:51:19 +00:00
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* Copyright 2019-2021 NXP
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2019-04-10 08:43:34 +00:00
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*/
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#ifndef __L1028A_COMMON_H
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#define __L1028A_COMMON_H
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
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/*
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* SMP Definitinos
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*/
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2020-06-01 19:53:26 +00:00
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#define CPU_RELEASE_ADDR secondary_boot_addr
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2019-04-10 08:43:34 +00:00
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2021-02-05 11:01:57 +00:00
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/* GPIO */
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2019-04-10 08:43:34 +00:00
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/* I2C */
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/* Serial Port */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
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/* Miscellaneous configurable options */
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/* Physical Memory Map */
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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2019-11-04 07:10:45 +00:00
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func(MMC, mmc, 1) \
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2020-03-10 03:31:05 +00:00
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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2019-04-10 08:43:34 +00:00
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#include <config_distro_bootcmd.h>
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2019-11-04 07:10:45 +00:00
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#define XSPI_NOR_BOOTCOMMAND \
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"run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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2019-04-10 08:43:34 +00:00
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#define SD_BOOTCOMMAND \
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2019-11-04 07:10:45 +00:00
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"run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#define SD2_BOOTCOMMAND \
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"run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
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2019-04-10 08:43:34 +00:00
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"env exists secureboot && esbc_halt;"
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#define OCRAM_NONSECURE_SIZE 0x00010000
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#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x8
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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2019-11-18 05:26:09 +00:00
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/* DisplayPort */
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#define DP_PWD_EN_DEFAULT_MASK 0x8
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2019-11-07 16:11:32 +00:00
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#ifdef CONFIG_NXP_ESBC
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2019-05-24 06:36:27 +00:00
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#include <asm/fsl_secure_boot.h>
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#endif
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2019-04-10 08:43:34 +00:00
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#endif /* __L1028A_COMMON_H */
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