2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2013-04-16 23:42:44 +00:00
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/*
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* (C) Copyright 2013 Atmel Corporation.
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* Josh Wu <josh.wu@atmel.com>
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*
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* Configuation settings for the AT91SAM9N12-EK boards.
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*/
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#ifndef __AT91SAM9N12_CONFIG_H_
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#define __AT91SAM9N12_CONFIG_H_
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
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/* Misc CPU related */
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/* LCD */
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#define LCD_BPP LCD_COLOR16
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#define LCD_OUTPUT_BPP 24
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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/*
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* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
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* leaving the correct space for initial global data structure above
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* that address while providing maximum stack area below.
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*/
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# define CONFIG_SYS_INIT_SP_ADDR \
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2017-09-14 03:07:42 +00:00
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(0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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2013-04-16 23:42:44 +00:00
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/* DataFlash */
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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2013-11-29 11:13:45 +00:00
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#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
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#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
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2017-07-29 01:31:42 +00:00
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#endif
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2013-04-16 23:42:44 +00:00
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console=console=ttyS0,115200\0" \
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2017-10-22 21:55:07 +00:00
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"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
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2013-04-16 23:42:44 +00:00
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"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
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"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
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2013-10-21 08:13:59 +00:00
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/* USB host */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_ATMEL
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2013-10-21 08:14:00 +00:00
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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2013-10-21 08:13:59 +00:00
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#endif
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2015-03-27 06:23:36 +00:00
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/* SPL */
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#define CONFIG_SPL_STACK 0x308000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20953f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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2013-04-16 23:42:44 +00:00
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#endif
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