2022-01-31 16:30:45 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __KONTRON_PITX_IMX8M_H
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#define __KONTRON_PITX_IMX8M_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
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#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
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#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x187FF0
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#define CONFIG_SPL_BSS_START_ADDR 0x00180000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x182000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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#endif
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/* ENET1 Config */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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#define ENV_MEM_LAYOUT_SETTINGS \
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2022-02-16 12:25:15 +00:00
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"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=0x42000000\0" \
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"fdt_addr_r=0x48000000\0" \
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"fdtoverlay_addr_r=0x49000000\0" \
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"ramdisk_addr_r=0x48080000\0" \
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"scriptaddr=0x40000000\0" \
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"pxefile_addr_r=0x40100000\0"
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2022-01-31 16:30:45 +00:00
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na) \
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func(PXE, pxe, 0)
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#include <config_distro_bootcmd.h>
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"image=Image\0" \
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"console=ttymxc2,115200\0" \
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"boot_fdt=try\0" \
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"fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
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"dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
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ENV_MEM_LAYOUT_SETTINGS \
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BOOTENV
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
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#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#endif
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