Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 07:34:31 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/include/pch.h

94 lines
2.5 KiB
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#ifndef __pch_h
#define __pch_h
dm: x86: Add a driver for Intel PCH7 At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:18 +00:00
#define PCH_RCBA 0xf0
#define BIOS_CTRL_BIOSWE BIT(0)
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
/* Operations for the Platform Controller Hub */
struct pch_ops {
/**
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:42 +00:00
* get_spi_base() - get the address of SPI base
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
*
* @dev: PCH device to check
* @sbasep: Returns address of SPI base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no SPI base)
*/
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:42 +00:00
int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
/**
* set_spi_protect() - set whether SPI flash is protected or not
*
* @dev: PCH device to adjust
* @protect: true to protect, false to unprotect
*
* @return 0 on success, -ENOSYS if not implemented
*/
int (*set_spi_protect)(struct udevice *dev, bool protect);
dm: pch: Add get_gpio_base op x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:43 +00:00
/**
* get_gpio_base() - get the address of GPIO base
*
* @dev: PCH device to check
* @gbasep: Returns address of GPIO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
dm: pch: Add get_io_base op On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:45 +00:00
/**
* get_io_base() - get the address of IO base
*
* @dev: PCH device to check
* @iobasep: Returns address of IO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int (*get_io_base)(struct udevice *dev, u32 *iobasep);
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
/**
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:42 +00:00
* pch_get_spi_base() - get the address of SPI base
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
*
* @dev: PCH device to check
* @sbasep: Returns address of SPI base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no SPI base)
*/
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:42 +00:00
int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
/**
* set_spi_protect() - set whether SPI flash is protected or not
*
* @dev: PCH device to adjust
* @protect: true to protect, false to unprotect
*
* @return 0 on success, -ENOSYS if not implemented
*/
int pch_set_spi_protect(struct udevice *dev, bool protect);
dm: pch: Add get_gpio_base op x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:43 +00:00
/**
* pch_get_gpio_base() - get the address of GPIO base
*
* @dev: PCH device to check
* @gbasep: Returns address of GPIO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
dm: pch: Add get_io_base op On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:45 +00:00
/**
* pch_get_io_base() - get the address of IO base
*
* @dev: PCH device to check
* @iobasep: Returns address of IO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int pch_get_io_base(struct udevice *dev, u32 *iobasep);
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:17 +00:00
#endif
Reference in a new issue Copy permalink