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u-boot/arch/arm/cpu/armv7/am33xx/clock_am43xx.c

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ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
/*
* clock_am43xx.c
*
* clocks for AM43XX based boards
* Derived from AM33XX based boards
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
ARM: AM43xx: Select clk source for Timer2 Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-10 09:32:17 +00:00
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
const struct dpll_regs dpll_mpu_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x560,
.cm_idlest_dpll = CM_WKUP + 0x564,
.cm_clksel_dpll = CM_WKUP + 0x56c,
.cm_div_m2_dpll = CM_WKUP + 0x570,
};
const struct dpll_regs dpll_core_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x520,
.cm_idlest_dpll = CM_WKUP + 0x524,
.cm_clksel_dpll = CM_WKUP + 0x52C,
.cm_div_m4_dpll = CM_WKUP + 0x538,
.cm_div_m5_dpll = CM_WKUP + 0x53C,
.cm_div_m6_dpll = CM_WKUP + 0x540,
};
const struct dpll_regs dpll_per_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x5E0,
.cm_idlest_dpll = CM_WKUP + 0x5E4,
.cm_clksel_dpll = CM_WKUP + 0x5EC,
.cm_div_m2_dpll = CM_WKUP + 0x5F0,
};
const struct dpll_regs dpll_ddr_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x5A0,
.cm_idlest_dpll = CM_WKUP + 0x5A4,
.cm_clksel_dpll = CM_WKUP + 0x5AC,
.cm_div_m2_dpll = CM_WKUP + 0x5B0,
ARM: AM43xx: clocks: Update DPLL details Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-10 09:32:20 +00:00
.cm_div_m4_dpll = CM_WKUP + 0x5B8,
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
};
void setup_clocks_for_console(void)
{
ARM: AM43xx: Fix UART clocks enabling After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-06-02 05:19:03 +00:00
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable UART0 */
clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
ARM: AM43xx: Fix UART clocks enabling After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-06-02 05:19:03 +00:00
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(&cmwkup->wkup_uart0ctrl);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
}
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
}
void enable_basic_clocks(void)
{
u32 *const clk_domains[] = {
&cmper->l3clkstctrl,
&cmper->l3sclkstctrl,
&cmper->l4lsclkstctrl,
&cmwkup->wkclkstctrl,
&cmper->emifclkstctrl,
0
};
u32 *const clk_modules_explicit_en[] = {
&cmper->l3clkctrl,
&cmper->l4lsclkctrl,
&cmper->l4fwclkctrl,
&cmwkup->wkl4wkclkctrl,
&cmper->l3instrclkctrl,
&cmper->l4hsclkctrl,
&cmwkup->wkgpio0clkctrl,
&cmwkup->wkctrlclkctrl,
&cmper->timer2clkctrl,
&cmper->gpmcclkctrl,
&cmper->elmclkctrl,
&cmper->mmc0clkctrl,
&cmper->mmc1clkctrl,
&cmwkup->wkup_i2c0ctrl,
&cmper->gpio1clkctrl,
&cmper->gpio2clkctrl,
&cmper->gpio3clkctrl,
ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control Schematic indicates GPIO5_7 is to be used for VTT regulator control rather than GPIO0_21 so modify enable_vtt_regulator to reflect this. Without this some boards will experience DDR3 corruption and fail to boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> [trini: Rework patch against mainline] Signed-off-by: Tom Rini <trini@ti.com>
2014-02-10 16:41:49 +00:00
&cmper->gpio4clkctrl,
&cmper->gpio5clkctrl,
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
&cmper->i2c1clkctrl,
ARM: AM43xx: clocks: Enable CPGMAC clock control Enable CPGMAC clock control for AM43xx to use ethernet in U-Boot Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-02-18 12:31:53 +00:00
&cmper->cpgmac0clkctrl,
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
&cmper->emiffwclkctrl,
&cmper->emifclkctrl,
&cmper->otfaemifclkctrl,
am43xx: Add qspi support Add QSPI definitions and clock configuration support. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-21 07:20:12 +00:00
&cmper->qspiclkctrl,
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
ARM: AM43xx: Select clk source for Timer2 Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-10 09:32:17 +00:00
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-30 06:06:29 +00:00
}
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