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u-boot/arch/riscv/lib/interrupts.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
/*
* Copyright (c) 2016-17 Microsemi Corporation.
* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
*
* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
*/
#include <common.h>
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-28 17:45:07 +00:00
#include <hang.h>
common: Move interrupt functions into a new header These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-14 19:57:41 +00:00
#include <irq_func.h>
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
static void show_regs(struct pt_regs *regs)
{
#ifdef CONFIG_SHOW_REGS
printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n",
regs->ra, regs->sp, regs->gp);
printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n",
regs->tp, regs->t0, regs->t1);
printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n",
regs->t2, regs->s0, regs->s1);
printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n",
regs->a0, regs->a1, regs->a2);
printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n",
regs->a3, regs->a4, regs->a5);
printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n",
regs->a6, regs->a7, regs->s2);
printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n",
regs->s3, regs->s4, regs->s5);
printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n",
regs->s6, regs->s7, regs->s8);
printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n",
regs->s9, regs->s10, regs->s11);
printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n",
regs->t3, regs->t4, regs->t5);
printf("T6: " REG_FMT "\n", regs->t6);
#endif
}
static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
{
static const char * const exception_code[] = {
"Instruction address misaligned",
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
"Load address misaligned",
"Load access fault",
"Store/AMO address misaligned",
"Store/AMO access fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved",
"Environment call from M-mode",
"Instruction page fault",
"Load page fault",
"Reserved",
"Store/AMO page fault",
};
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
if (code < ARRAY_SIZE(exception_code))
printf("Unhandled exception: %s\n", exception_code[code]);
else
printf("Unhandled exception code: %ld\n", code);
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval);
show_regs(regs);
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
hang();
}
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
int interrupt_init(void)
{
return 0;
}
/*
* enable interrupts
*/
void enable_interrupts(void)
{
}
/*
* disable interrupts
*/
int disable_interrupts(void)
{
return 0;
}
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
{
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
ulong is_irq, irq;
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
if (is_irq) {
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
case IRQ_S_TIMER:
timer_interrupt(0); /* handle timer interrupt */
break;
default:
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
_exit_trap(cause, epc, tval, regs);
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
break;
};
} else {
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
_exit_trap(cause, epc, tval, regs);
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
}
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
return epc;
}
/*
*Entry Point for PLIC Interrupt Handler
*/
__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
{
}
__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
{
}
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