2018-12-16 22:25:22 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* JZ4780 definitions
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*
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* Copyright (c) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*/
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#ifndef __JZ4780_H__
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#define __JZ4780_H__
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/* AHB0 BUS Devices */
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#define DDRC_BASE 0xb3010000
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/* AHB2 BUS Devices */
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#define NEMC_BASE 0xb3410000
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#define BCH_BASE 0xb34d0000
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/* APB BUS Devices */
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#define CPM_BASE 0xb0000000
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#define TCU_BASE 0xb0002000
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#define WDT_BASE 0xb0002000
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#define GPIO_BASE 0xb0010000
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#define UART0_BASE 0xb0030000
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#define UART1_BASE 0xb0031000
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#define UART2_BASE 0xb0032000
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#define UART3_BASE 0xb0033000
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#define MSC0_BASE 0xb3450000
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#define MSC1_BASE 0xb3460000
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#define MSC2_BASE 0xb3470000
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/*
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* GPIO
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*/
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/* n = 0,1,2,3,4,5 */
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#define GPIO_PXPIN(n) (0x00 + (n) * 0x100)
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#define GPIO_PXINT(n) (0x10 + (n) * 0x100)
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#define GPIO_PXINTS(n) (0x14 + (n) * 0x100)
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#define GPIO_PXINTC(n) (0x18 + (n) * 0x100)
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#define GPIO_PXMASK(n) (0x20 + (n) * 0x100)
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#define GPIO_PXMASKS(n) (0x24 + (n) * 0x100)
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#define GPIO_PXMASKC(n) (0x28 + (n) * 0x100)
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#define GPIO_PXPAT1(n) (0x30 + (n) * 0x100)
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#define GPIO_PXPAT1S(n) (0x34 + (n) * 0x100)
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#define GPIO_PXPAT1C(n) (0x38 + (n) * 0x100)
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#define GPIO_PXPAT0(n) (0x40 + (n) * 0x100)
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#define GPIO_PXPAT0S(n) (0x44 + (n) * 0x100)
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#define GPIO_PXPAT0C(n) (0x48 + (n) * 0x100)
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#define GPIO_PXFLG(n) (0x50 + (n) * 0x100)
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#define GPIO_PXFLGC(n) (0x54 + (n) * 0x100)
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#define GPIO_PXOEN(n) (0x60 + (n) * 0x100)
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#define GPIO_PXOENS(n) (0x64 + (n) * 0x100)
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#define GPIO_PXOENC(n) (0x68 + (n) * 0x100)
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#define GPIO_PXPEN(n) (0x70 + (n) * 0x100)
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#define GPIO_PXPENS(n) (0x74 + (n) * 0x100)
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#define GPIO_PXPENC(n) (0x78 + (n) * 0x100)
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#define GPIO_PXDS(n) (0x80 + (n) * 0x100)
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#define GPIO_PXDSS(n) (0x84 + (n) * 0x100)
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#define GPIO_PXDSC(n) (0x88 + (n) * 0x100)
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/* PLL setup */
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#define JZ4780_SYS_EXTAL 48000000
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2022-07-10 15:15:12 +00:00
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#define JZ4780_SYS_MEM_SPEED (1200 * 1000000)
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2018-12-16 22:25:22 +00:00
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#define JZ4780_SYS_MEM_DIV 3
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#define JZ4780_SYS_AUDIO_SPEED (768 * 1000000)
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#define JZ4780_APLL_M 1
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#define JZ4780_APLL_N 1
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#define JZ4780_APLL_OD 1
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#define JZ4780_MPLL_M (JZ4780_SYS_MEM_SPEED / JZ4780_SYS_EXTAL * 2)
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#define JZ4780_MPLL_N 2
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#define JZ4780_MPLL_OD 1
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#define JZ4780_EPLL_M (JZ4780_SYS_AUDIO_SPEED * 2 / JZ4780_SYS_EXTAL)
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#define JZ4780_EPLL_N 1
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#define JZ4780_EPLL_OD 2
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#define JZ4780_VPLL_M ((888 * 1000000) * 2 / JZ4780_SYS_EXTAL)
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#define JZ4780_VPLL_N 1
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#define JZ4780_VPLL_OD 2
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#ifndef __ASSEMBLY__
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u32 sdram_size(int bank);
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const u32 jz4780_clk_get_efuse_clk(void);
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void jz4780_clk_ungate_ethernet(void);
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void jz4780_clk_ungate_mmc(void);
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void jz4780_clk_ungate_uart(const unsigned int uart);
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void jz4780_efuse_read(size_t addr, size_t count, u8 *buf);
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void jz4780_efuse_init(u32 ahb2_rate);
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void jz4780_tcu_wdt_start(void);
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#ifdef CONFIG_SPL_BUILD
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int jz_mmc_init(void __iomem *base);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __JZ4780_H__ */
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