u-boot/arch/arm/dts/zynq-syzygy-hub.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * SYZYGY Hub DTS
 *
 *  Copyright (C) 2011 - 2015 Xilinx
 *  Copyright (C) 2017 Opal Kelly Inc.
 */
/dts-v1/;
/include/ "zynq-7000.dtsi"

/ {
	model = "SYZYGY Hub";
	compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart0;
		mmc0 = &sdhci0;
		i2c0 = &i2c1;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	chosen {
		bootargs = "";
		stdout-path = "serial0:115200n8";
		xlnx,eeprom = &eeprom;
	};

	usb_phy0: phy0 {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio0 47 1>;
	};
};

&clkc {
	ps-clk-frequency = <50000000>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@0 {
		reg = <0>;
		device_type = "ethernet-phy";
	};
};

&i2c1 {
	status = "okay";
	eeprom: eeprom@57 {
		compatible = "atmel,24c08"; /* not sure if this is correct */
		reg = <0x57>;
	};
};

&sdhci0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&uart0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "otg";
	usb-phy = <&usb_phy0>;
};